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Deepak Bharadwaj

from Fremont, CA
Age ~47
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Also known as:
Peepak Braradwaj
Phone and address:
36423 Sea Breeze Cmn, Fremont, CA 94536
Connected to:
Akanksha Bharadwaj, 33Amar K Bharadwaj, 75Anagha Bharadwaj, 32Anoopendra Bharadwaj, 69Manish S Bharadwaj, 54Raghav Bharadwaj, 38Raghavan Bharadwaj, 52Raj T Bharadwaja, 84Sai K Bharadwaj, 41Sharada Bharadwaj, 54

Deepak Bharadwaj Phones & Addresses

  • 36423 Sea Breeze Cmn, Fremont, CA 94536
  • Milpitas, CA
  • Sandy, UT
  • Draper, UT
  • Boise, ID
  • Tucson, AZ

Resumes

Resumes

Deepak Bharadwaj Photo 1

Technologist

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Location:
36423 Sea Breeze Cmn, Fremont, CA 94536
Industry:
Electrical/Electronic Manufacturing
Work:
Sandisk Western Digital Brand
Technologist
Sandisk Jul 1, 2014 - Jun 2017
Staff Product Engineer
Im Flash Technologies Aug 2009 - Jun 2014
Probe Functional Engineer
Micron Technology Aug 2007 - Mar 2009
Product Engineer-Dram Engineering
Micron Technology Mar 2005 - Aug 2007
Product Engineer-Nand Flash
Education:
Brigham Young University Marriott School of Business 2011 - 2013
Master of Business Administration, Masters, Leadership, Marketing, Management, Project Management University of Arizona 2002 - 2005
Masters, Computer Engineering Modern School 1982 - 1995
Karnataka Law College, Dharwad
Bachelor of Engineering, Bachelors, Communication, Electronics
Skills:
Simulations
Verilog
Project Management
Semiconductor Characterization
Ate Testers
Strategy
Brand Management
Marketing
Product Development
Device Characterization
Jmp
Data Mining
Testing
Yield
Perl
Test Engineering
Dram
Debugging
Silicon
Ic
Semiconductors
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Deepak Bharadwaj

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Deepak Bharadwaj Photo 3

Deepak Bharadwaj

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Deepak Bharadwaj Photo 4

Deepak Bharadwaj

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Deepak Bharadwaj Photo 5

Deepak Bharadwaj

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Publications

Us Patents

Memory Controller For Resolving String To String Shorts

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US Patent:
20210389901, Dec 16, 2021
Filed:
Jun 10, 2020
Appl. No.:
16/898098
Inventors:
- San Jose CA, US
Rajan Paudel - Dublin CA, US
Deepak Bharadwaj - Fremont CA, US
International Classification:
G06F 3/06
G11C 16/04
G11C 16/10
Abstract:
A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory interface configured to interface with a memory having a plurality of memory blocks. Each memory block has a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one of the memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the string to string shorts in response to determining that the one of the memory blocks has the string to string shorts.

Apparatus And Methods For Reticle Configuration

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US Patent:
20190187553, Jun 20, 2019
Filed:
Dec 18, 2017
Appl. No.:
15/845456
Inventors:
- Plano TX, US
Jianhua Zhu - Saratoga CA, US
Srikar Peesari - San Jose CA, US
Kirubakaran Periyannan - Santa Clara CA, US
Avinash Rajagiri - San Jose CA, US
Shantanu Gupta - Milpitas CA, US
Jagdish Sabde - Fremont CA, US
Ashish Ghai - San Jose CA, US
Deepak Bharadwaj - Fremont CA, US
Assignee:
SANDISK TECHNOLOGIES LLC - Plano TX
International Classification:
G03F 1/50
Abstract:
An apparatus is provided that includes a reticle including a die, the reticle configured to increase a number of partial die that can be successfully used as partially operable die.

Partial Memory Die With Inter-Plane Re-Mapping

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US Patent:
20190129861, May 2, 2019
Filed:
Oct 31, 2017
Appl. No.:
15/799643
Inventors:
- Plano TX, US
Srikar Peesari - San Jose CA, US
Kirubakaran Periyannan - Santa Clara CA, US
Avinash Rajagiri - San Jose CA, US
Shantanu Gupta - Milpitas CA, US
Jagdish Sabde - Fremont CA, US
Ashish Ghai - San Jose CA, US
Deepak Bharadwaj - Santa Clara CA, US
Assignee:
SANDISK TECHNOLOGIES LLC - Plano TX
International Classification:
G06F 12/10
G06F 3/06
G11C 16/04
G11C 13/00
G11C 11/16
Abstract:
A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

Partial Memory Die

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US Patent:
20190130978, May 2, 2019
Filed:
Oct 31, 2017
Appl. No.:
15/799666
Inventors:
- Plano TX, US
Srikar Peesari - San Jose CA, US
Kirubakaran Periyannan - Santa Clara CA, US
Avinash Rajagiri - San Jose CA, US
Shantanu Gupta - Milpitas CA, US
Jagdish Sabde - Fremont CA, US
Ashish Ghai - San Jose CA, US
Deepak Bharadwaj - Santa Clara CA, US
Sukhminder Singh Lobana - Fremont CA, US
Shrikar Bhagath - San Jose CA, US
Assignee:
SANDISK TECHNOLOGIES LLC - Plano TX
International Classification:
G11C 16/10
G11C 16/04
H01L 27/11529
H01L 27/11573
Abstract:
A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.
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Deepak Bharadwaj from Fremont, CA, age ~47 Get Report