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Dean K Nobunaga

from Cupertino, CA
Age ~59
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Also known as:
Dean Te Nobunaga
Phone and address:
10300 Farallone Dr, Cupertino, CA 95014
(408) 253-7803
Related to:
Marie Owyang, 97Donna OwyangAlyssa O Nobunaga, 52Walter M OwyangVirginia G OwyangAlexander M Owyang, 54
Connected to:
Mihaela V Nocasian, 59Elyse R Noccioli, 37Jacqueline H Noccioli, 67Diane E Nocco, 53Aaron L Noce, 41Anette R Noce, 96Christian P Noce, 57Dennis J Noce, 70Diane M Noce, 70Erik K Noce, 45

Dean Nobunaga Phones & Addresses

  • 10300 Farallone Dr, Cupertino, CA 95014 (408) 253-7803
  • 6360 Myrtlewood Dr, Cupertino, CA 95014 (408) 253-7803
  • 355 Wolfe Rd, Sunnyvale, CA 94085
  • Fremont, CA
  • Newark, CA
  • Santa Clara, CA
  • 10300 Farallone Dr, Cupertino, CA 95014 (408) 621-5589

Work

Company: Micron technology Jan 2006 to Aug 2012 Position: Design manager

Education

School / High School: 'Iolani School

Skills

Cmos • Ic • Semiconductors • Asic • Verilog

Industries

Semiconductors

Resumes

Resumes

Dean Nobunaga Photo 1

Director Of Design Engineering

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Micron Technology Jan 2006 - Aug 2012
Design Manager
Avalanche Technology Inc. Jan 2006 - Aug 2012
Director of Design Engineering
Education:
'Iolani School
University of Colorado Boulder
Bachelors, Bachelor of Science, Electronics Engineering Santa Clara University
Master of Science, Masters, Electronics Engineering
Skills:
Cmos
Ic
Semiconductors
Asic
Verilog

Publications

Us Patents

Differential Sensing In A Memory Using Two Cycle Pre-Charge

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US Patent:
6496434, Dec 17, 2002
Filed:
Aug 25, 2000
Appl. No.:
09/648706
Inventors:
Dean Nobunaga - Sunnyvale CA
Assignee:
Micron Technology Inc. - Boise ID
International Classification:
G11C 700
US Classification:
365203, 36518513, 36518525, 365207
Abstract:
A memory device has been described that can read data stored in non-volatile memory cells using a differential voltage sensing technique. The memory includes a differential voltage sensing circuit having two input nodes. The nodes of the sensing circuit are pre-charged to different initial voltage levels prior to reading the memory cell. The nodes are pre-charged by charge sharing multiple bit lines during two charge sharing cycles. During a first cycle, both nodes are pre-charged to a common voltage level. During the second cycle, a reference node is further charge shared to reduce its voltage. A selected node that is coupled to a memory cell to be read is pre-charged to a higher value than the second sensing node. After a word line coupled to the memory cell is activated, the initial differential voltage between the sensing nodes will remain if the memory cell is programmed such that it does not conduct current in response to the word line signal. If the memory cell is not programmed, the memory cell will discharge the selected sensing node to provide a different differential voltage to be sensed.

Differential Sensing In A Memory

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US Patent:
6507525, Jan 14, 2003
Filed:
Aug 25, 2000
Appl. No.:
09/648723
Inventors:
Dean Nobunaga - Sunnyvale CA
Frankie F. Roohparvar - Miltitas CA
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 700
US Classification:
365203, 36518525, 36518911
Abstract:
A memory device can read data stored in memory cells using a differential voltage sensing technique. The memory includes a differential voltage sensing circuit having two input nodes. The nodes of the sensing circuit are pre-charged to different initial voltage levels prior to reading the memory cell. The nodes are pre-charged by charge sharing multiple bit lines. A selected node that is coupled to a memory cell to be read is pre-charged to a higher value than the second sensing node. After a word line coupled to the memory cell is activated, the initial differential voltage between the sensing nodes will remain if the memory cell is programmed such that it does not conduct current in response to the word line signal. If the memory cell is not programmed, the memory cell will discharge the selected sensing node to provide a different differential voltage to be sensed.

Read Compression In A Memory

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US Patent:
6584025, Jun 24, 2003
Filed:
Sep 21, 2001
Appl. No.:
09/957733
Inventors:
Frankie F. Roohparvar - Milpitas CA
Dean Nobunaga - Sunnyvale CA
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 700
US Classification:
365201, 36518905
Abstract:
A memory device has multiple selectable read data paths. Some of the read data paths include compression circuitry to compress data and decrease test time by testing multiple memories in parallel and/or multiple array banks from the same memory in parallel. A non-compression read path is provided to by-pass the compression circuitry. During memory read operations, therefore, data can be coupled to output buffers without being subjected to delays through a compression circuit. A first compression path can be selected to couple 16 bits from 1 memory array bank to 4 output connections. A second compression path can be selected to couple 64 bits from 4 memory array banks to 4 output connections.

Distributed Fifo In Synchronous Memory

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US Patent:
6678201, Jan 13, 2004
Filed:
Apr 8, 2002
Appl. No.:
10/118281
Inventors:
Frankie Fariborz Roohparvar - Milpitas CA
Dean Nobunaga - Cupertino CA
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 700
US Classification:
365221, 36518905, 365207, 365233, 365239
Abstract:
A synchronous memory device includes a distributed FIFO buffer in a read path. Buffer stages of the FIFO are located at remote ends of an internal data bus. The time needed for loading the first FIFO stage is reduced and allows shorter clock cycle times for some memory read operations.

Read Compression In A Memory

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US Patent:
6693841, Feb 17, 2004
Filed:
Jan 31, 2003
Appl. No.:
10/356097
Inventors:
Frankie F. Roohparvar - Milpitas CA
Dean Nobunaga - Sunnyvale CA
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 800
US Classification:
36523003, 36518905
Abstract:
A memory device has multiple selectable read data paths. Some of the read data paths include compression circuitry to compress data and decrease test time by testing multiple memories in parallel and/or multiple array banks from the same memory in parallel. A non-compression read path is provided to by-pass the compression circuitry. During memory read operations, therefore, data can be coupled to output buffers without being subjected to delays through a compression circuit. A first compression path can be selected to couple 16 bits from 1 memory array bank to 4 output connections. A second compression path can be selected to couple 64 bits from 4 memory array banks to 4 output connections.

Adjustable Timing Circuit Of An Integrated Circuit By Selecting And Moving Clock Edges Based On A Signal Propagation Time Stored In A Programmable Non-Volatile Fuse Circuit

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US Patent:
6877100, Apr 5, 2005
Filed:
Aug 25, 2000
Appl. No.:
09/648857
Inventors:
Dean Nobunaga - Sunnyvale CA, US
Frankie F. Roohparvar - Miltitas CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H04L007/00
US Classification:
713400, 326 93, 713401
Abstract:
An adjustable timing circuit includes non-volatile programmable fuses and adjustable delay elements. A propagation time of the delay element is selected with the non-volatile fuses. The delay element can include capacitors that are selectively coupled to a propagation path in response to the data stored in the fuse circuits. In one embodiment, data stored in the programmed fuses is copied to volatile latch circuits for use during operation of the timing circuit. The adjustable timing circuit can be provided in any integrated circuit, but is particularly useful in memory devices. The timing system allows for testing and fine-tuning signal processing in the integrated circuits.

Method And Apparatus Using Parasitic Capacitance For Synchronizing Signals A Device

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US Patent:
7080275, Jul 18, 2006
Filed:
Aug 12, 2002
Appl. No.:
10/216439
Inventors:
Ebrahim Abedifard - Sunnyvale CA, US
Frankie Roohparvar - Milpitas CA, US
Dean Nobunaga - Cupertino CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G06F 1/12
US Classification:
713401, 713400, 713600, 365196
Abstract:
A method and apparatus for compensating address and control lines to account for clock delays within a memory device is disclosed. Latches are located directly within a the storage area of the memory device, so that the parasitic capacitance inherent within the address and control lines can be advantageously employed for introducing delay. The parasitic delay enables the clock, address, and control lines to be synchronized, yet does not require introducing delay blocks and so the overall speed of the memory device is improved.

Adjustable Timing Circuit Of An Integrated Circuit

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US Patent:
7130227, Oct 31, 2006
Filed:
Sep 1, 2005
Appl. No.:
11/217921
Inventors:
Dean Nobunaga - Sunnyvale CA, US
Frankie F. Roohparvar - Miltitas CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 15/02
US Classification:
365194, 365149
Abstract:
An adjustable timing circuit includes non-volatile programmable fuses and adjustable delay elements. A propagation time of the delay element is selected with the non-volatile fuses. The delay element can include capacitors that are selectively coupled to a propagation path in response to the data stored in the fuse circuits. In one embodiment, data stored in the programmed fuses is copied to volatile latch circuits for use during operation of the timing circuit. The adjustable timing circuit can be provided in any integrated circuit, but is particularly useful in memory devices. The timing system allows for testing and fine-tuning signal processing in the integrated circuits.
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Dean K Nobunaga from Cupertino, CA, age ~59 Get Report