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Dawson L Yee

from Medina, WA
Age ~61
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Also known as:
Dawson Wendy Yee, Lang Yee Dawson, Yee L Dawson
Phone and address:
8232 Overlake Dr W, Medina, WA 98039
(425) 454-0808
Related to:
Savanna Yee, 27L LinHsi Lin, 34Weilai Lin, 87Fenju Lin, 59George Lin, 33Yan O Lin, 61George YeeWendy Y Lyee, 62Wen Yang, 63
Connected to:
Adriel S Yee, 42Alpha Yee, 32Anita D Yee, 53Bik Y Yee, 88Bridget F Yee, 67Carolyn F Yee, 77Caryn K Yee, 57Cathy W Yee, 47Ceci Z Yee, 65Cesar I Yee, 49

Dawson Yee Phones & Addresses

  • 8232 Overlake Dr W, Medina, WA 98039 (425) 454-0808
  • Clyde Hill, WA
  • Redmond, WA
  • Beaverton, OR
  • Portland, OR
  • Kirkland, WA
  • Kiona, WA
  • 8232 Overlake Dr W, Medina, WA 98039

Education

Degree: Associate degree or higher

Publications

Us Patents

Flexible Connection System

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US Patent:
6369333, Apr 9, 2002
Filed:
Feb 13, 1998
Appl. No.:
09/023531
Inventors:
Dawson Yee - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01R 909
US Classification:
174261, 174207, 257706, 301700, 301809, 439 92
Abstract:
A method and apparatus for a connection system to a substrate is provided. The system includes a substrate having a mounting hole to permit an object to be coupled to the substrate. The substrate further includes a conductive pattern around the mounting hole on the substrate. The conductive pattern is designed to contact an interface, and selectively couple a ground signal to the object coupled to the substrate.

Resistance Based Keyboard Key Discrimination

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US Patent:
6577250, Jun 10, 2003
Filed:
May 19, 2000
Appl. No.:
09/574216
Inventors:
Dawson Yee - Redmond WA
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
H03K 1794
US Classification:
341 26, 345178, 379368, 341 34
Abstract:
In place of a conventional nÃm sense line/drive line matrix for keyboard key detection, discrimination between keyboard keys is carried out with one or more current divider or voltage divider circuits, with the result that the number of necessary IC pin connections may be reduced. The keyboard key switches are arranged into one or more current divider or voltage divider circuits. In a current divider embodiment, the key switches of each circuit are arranged in parallel with each other at respective points along a resistive switch line extending from Vcc to ground. When closed by key depression, the switches provide shortened paths from Vcc to ground, thus resulting in a current division effect. A voltage along the line is input to an A/D converter of a micro-controller which performs keyboard key discrimination. In a voltage divider embodiment, the key switches within a circuit are arranged in parallel with each other between (1) respective points along a resistive switch line extending from Vcc to ground; and (2) an A/D converter of a micro-controller.

Keyboard Key Discrimination Based On Time Division Multiplexing

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US Patent:
6621484, Sep 16, 2003
Filed:
Jun 27, 2000
Appl. No.:
09/604688
Inventors:
Dawson Yee - Redmond WA
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G09G 500
US Classification:
345168, 345169, 341 26
Abstract:
A keyboard switch matrix arrangement provides keyboard key discrimination utilizing simultaneous groupings of drive line combinations and sense line combinations (time division multiplexing) to discriminate between keyboard keys with substantially fewer total drive and sense lines than a conventional switch matrix, thereby substantially reducing the number of required IC pin connections. The invention permits given sense lines to sense more than one drive line for a valid key press duration (i. e. , key actuation), and given drive lines to drive more than one sense line for a given valid key press duration. In this manner, and through utilization of time division multiplexing, the switch capacity of a matrix with a given number of drive lines and sense lines can be substantially increased.

Keyboard Key Discrimination Employing Drive Line/Sense Line Combinations And Accomodating Simultaneous Key Press Conditions

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US Patent:
6630927, Oct 7, 2003
Filed:
Feb 15, 2001
Appl. No.:
09/783285
Inventors:
Nathan C. Sherman - Sammamish WA
Dawson Yee - Redmond WA
Christopher R. Bagin - Arlington MA
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G09G 500
US Classification:
345168, 341 20, 341 21
Abstract:
In a conventional 8Ã17 drive line/sense line keyboard switch matrix, a one-to-one correspondence between keyboard key switches and drive line/sense line pairs, together with a sequential driving of the drive lines, permits discrimination between 8Ã17=136 keyboard keys with 25 I/O pins. In contrast, the present invention utilizes drive line/sense line combinations to discriminate between keyboard keys with fewer total drive and sense lines, thereby reducing the number of required IC pin connections. In addition to achieving a reduction in the number of required pin connections, particular drive line/sense line contact patterns (e. g. , a 2/2 pattern), and an associated subtraction algorithm, allow for efficient layouts of the drive lines and sense lines on respective membrane switch layers, a reduction of detection errors arising from inadvertent illegal simultaneous key presses, and discrimination of âspecialâ simultaneous key press conditions.

Display Controller Permitting Connection Of Multiple Displays With A Single Video Cable

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US Patent:
7136042, Nov 14, 2006
Filed:
Oct 29, 2002
Appl. No.:
10/284045
Inventors:
Chad L. Magendanz - Issaquah WA, US
William J. Westerinen - Sammamish WA, US
Dawson Yee - Clyde Hill WA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G09G 3/36
G09G 5/00
US Classification:
345100, 345 11, 345 31
Abstract:
A display controller that permits more than one display to be operated by a single cable and a single display adapter. The display controller provides custom EDID information to a computer to which it is attached. The custom EDID information may include information about the single virtual display surface provided by all displays, and may include information about each of the individual monitors or displays, including the location of the individual displays in the single composite display surface. The single composite display surface may be utilized by computers that are not capable of recognizing the EDID for the multiple display system. If the computer does recognize the EDID for the multiple display system, the operating system of the computer and/or applications running on the computer may understand and utilize the heterogeneous nature of the display surface and may optimize display quality and presentation for a user.

Monitor Interconnect Compensation By Signal Calibration

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US Patent:
7154493, Dec 26, 2006
Filed:
Mar 13, 2003
Appl. No.:
10/386436
Inventors:
Dawson Yee - Clyde Hill WA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G09G 5/00
US Classification:
345211, 345213, 348189
Abstract:
To improve the performance of a standard monitor interconnect, e. g. , a VGA monitor interconnect, a display adaptor of a computer device generates reference signal patterns which are used to calibrate the signals received by an interconnected display monitor. The monitor receives the reference signal patterns from the computer over the interconnect with the analog display signals, e. g. , during the blanking intervals of the signals, and adjusts the signals based upon a detected deviation of the reference signals from corresponding control values. In one embodiment, the computer device generates and sends reference signal patterns if it receives from the monitor confirmation that it is equipped to perform calibration based upon received reference signal patterns, and operates normally (without reference signal pattern generation) otherwise.

Method And System For Reducing Latency In Transferring Captured Image Data By Utilizing Burst Transfer After Threshold Is Reached

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US Patent:
7254665, Aug 7, 2007
Filed:
Jun 16, 2004
Appl. No.:
10/870778
Inventors:
Dawson L. Yee - Clyde Hill WA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06F 13/00
G09G 5/00
G09G 5/08
G06K 9/18
US Classification:
710710, 710 5, 345156, 345163, 345173, 345346, 715861, 715863, 715865
Abstract:
Video sensor data are communicated to a memory of a computer system with reduced latency. Upon receiving data from the video sensor, the data are stored until a desired transfer quantity is reached. The transfer quantity is equivalent to a width of a system memory or cache. When the number of data readings detected reaches an integer multiple of the transfer quantity, a bus request is issued. When the request is granted, the data readings are transferred to system memory in a burst mode. Because the transfer quantity is equivalent to a width of a system memory or cache, at least one line of memory or cache is filled during the course of the transfer. Thus, efficient use is made of bus resources. Also, because the processor can access a full line of system memory or cache without waiting for an additional fetch operation, processor resources are used efficiently.

System And Method For Reducing Latency In Display Of Computer-Generated Graphics

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US Patent:
7259758, Aug 21, 2007
Filed:
Jun 21, 2004
Appl. No.:
10/872941
Inventors:
Dawson L. Yee - Clyde Hill WA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G09G 5/00
US Classification:
345204, 345215
Abstract:
An interactive display system wherein a projector receives signals from a graphics source in a manner that reduces latency in images projected onto a display surface. The signals include a pixel clock signal, pixel attribute signals, and synchronization signals. The pixel clock signal is used to clock sample and hold registers at the projector to preserve the pixel attribute signals received from the graphics source. The preserved pixel attribute signals, along with position signals corresponding to the synchronization signals, are presented directly to the projector. Parameters of the projector are known, and all gain, gamma correction, and scaling are performed before the signals are provided by the graphics source. Thus, it is unnecessary to digitize, store, adjust, or otherwise process pixel attribute signals at the projector, which simplifies processing of the graphics signals and reduces latency in generating the image in response to an input on the display surface.
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Dawson L Yee from Medina, WA, age ~61 Get Report