David A Stronks

20130328755, Dec 12, 2013

Aug 31, 2012

13/601516

David A. Stronks - San Jose CA, US
Hopil Bae - Sunnyvale CA, US

APPLE INC. - Cupertino CA

G09G 3/36

345 87

Systems, methods, and devices are provided to calibrate an electronic display to reduce or eliminate mura artifacts. Such mura artifacts may be due to differential behavior of multiple common voltage layers (VCOMs) of the display. One method for reducing or eliminating such muras may involve setting pixels of an electronic display to a gray level and setting an operating parameter of the liquid crystal display to a starting value. An image of the pixels may be captured. Using the image, an average luminance of the pixels may be determined and the image may be amplified around the average luminance to enhance contrast of the image. When the amplified image substantially does not indicates the presence of a mura, the value of the operating parameter may be stored in the electronic display.

20130328758, Dec 12, 2013

Jun 8, 2012

13/492782

David A. STRONKS - Sunnyvale CA, US
Hopil BAE - Cupertino CA, US

Apple Inc. - Cupertino CA

G09G 3/36

345 88, 345 92

A differential subpixel of a display apparatus includes a first drive transistor and a second drive transistor. The first drive transistor has a first drive signal with a first polarity and the second drive transistor has a second drive signal with a second polarity. The first polarity is opposed to the second polarity and the first drive signal and the second drive signal are configured to be driven with complementary differential signals.

20130328759, Dec 12, 2013

Aug 31, 2012

13/601529

David A. Stronks - San Jose CA, US
Hopil Bae - Sunnyvale CA, US

APPLE INC. - Cupertino CA

G09G 3/36
G02F 1/13

345 89, 349187

Systems and methods for calibrating an electronic display to reduce or eliminate artifacts are provided. One method for reducing or eliminating artifacts may involve baking the operational—but not yet fully calibrated—electronic display to reduce stray charge on the electronic display. After baking the display, the electronic display may be calibrated to reduce or eliminate flicker and/or mura artifacts

20130328843, Dec 12, 2013

Oct 17, 2012

13/654231

David A. Stronks - San Jose CA, US
Hopil Bae - Sunnyvale CA, US

APPLE INC. - Cupertino CA

G09G 3/36
G09G 5/00
G09G 5/10

345207, 345 87, 345690

Systems, methods, and devices for calibrating an electronic display to reduce or eliminate a mura artifact are provided. The mura artifact may be due to differential behavior of common voltage layers (VCOMs) in the electronic display. One method for reducing or eliminating the mura artifact may involve setting pixels of the electronic display to a first gray level and measuring a luminance difference between light and dark areas of a mura artifact on the electronic display. A value of an operating parameter of the electronic display may be adjusted while monitoring the luminance difference measurement. A value of the operating parameter that causes the luminance difference measurement to be within a specified range of acceptable luminance difference measurement values may be stored in the electronic display.

20130328847, Dec 12, 2013

Oct 17, 2012

13/654242

Hopil Bae - Sunnyvale CA, US
Sang Y. Youn - Cupertino CA, US
Yafei Bi - Palo Alto CA, US
Wei H. Yao - Palo Alto CA, US
David A. Stronks - San Jose CA, US

APPLE INC. - Cupertino CA

G09G 5/00

345211

Methods and devices employing mura prevention circuitry, are provided. In one example, a method may include supplying a first voltage pathway between a common electrode driver and a common electrode of an electronic display device and supplying a second voltage pathway between the common electrode driver and ground. Mura prevention circuitry may be supplied that activates the first voltage pathway when the electronic display device is turned on and an activation gate signal is provided from a gate corresponding to the common electrode driver. Further, the mura prevention circuitry may activate the second voltage pathway when the electronic display device is turned off or no activation gate signal is provided from the gate corresponding to the common electrode driver.

20130329057, Dec 12, 2013

Aug 31, 2012

13/601801

David A. Stronks - San Jose CA, US
Hopil Bae - Sunnyvale CA, US

APPLE INC. - Cupertino CA

H04N 17/00
H01R 43/00
G09G 5/10

348189, 345690, 295921, 29825, 348E17001

Systems and methods for calibrating an electronic display to reduce or eliminate a mura artifact are provided. The mura artifact may be due to differential behavior of common voltage layers (VCOMs) in the electronic display. One method for reducing or eliminating the mura artifact may involve turning on an electronic display and programming pixels the electronic display to a uniform gray level. An initial luminance value may be determined and, after waiting a period of time, a subsequent luminance of the pixels may be measured. When a difference between the subsequent luminance and initial luminance is within a threshold, the mura artifact may be understood to have settled and the electronic display may be calibrated.

20130215578, Aug 22, 2013

Sep 27, 2012

13/629542

David A. STRONKS - Sunnyvale CA, US
Ahmad Al- Dahle - San Jose CA, US
Wei H. Yao - Palo Alto CA, US

Apple Inc. - Cupertino CA

H05K 1/18
H05K 3/00

361749, 361748, 156297, 1563066, 156247

A method of creating a resistive pathway for an electronic assembly is disclosed. In one embodiment, the pathway can be formed with a resistive film in conjunction with a conductive adhesive and a coverlay. In another embodiment, the resistive film, the conductive adhesive and the coverlay can be relatively transparent. In yet another embodiment, the resistive pathway can couple directly with traces on an electronic assembly saving space and easing assembly.

20180062508, Mar 1, 2018

Oct 30, 2017

15/798193

- Cupertino CA, US
David A. STRONKS - San Jose CA, US
Hopil BAE - Sunnyvale CA, US
Kingsuk BRAHMA - San Francisco CA, US
Wei Hsin YAO - Palo Alto CA, US
Yafei BI - Los Altos Hills CA, US
Yingxuan LI - Saratoga CA, US

H02M 3/07
H01L 23/64
G06F 3/044
G06F 1/32
G06F 3/041

A charge pump that can be configured to operate in a first mode and a second mode is disclosed. The charge pump can comprise a charging capacitor coupled to a first node and configured to transfer a first DC voltage to the first node. The charge pump can also comprise a first output node and a second output node coupled to the first node. During the first mode, the first output node can be configured to output a second DC voltage based on the first DC voltage, and the second output node can be configured to output a third DC voltage based on the first DC voltage. During the second mode, the first output node can be configured to output the second DC voltage, and the second output node can be configured to output an AC voltage, the AC voltage being offset by the third DC voltage.