David R Shreiner

7716683, May 11, 2010

Dec 30, 2004

11/027752

Hansong Zhang - Cupertino CA, US
David Shreiner - Mountain View CA, US

Graphics Properties Holdings, Inc. - Newark CA

G06F 9/44
G09G 5/39

719323, 719324, 345531

A method and apparatus forward a hardware call from a driver to graphics hardware via a virtual connection. Specifically, the method and apparatus process graphical data in a system having the driver, which produces a hardware call for the controlling the operation of the graphics hardware. As noted above, the method and apparatus first establish the virtual connection between the driver and the graphics hardware. Next, the hardware call is forwarded to the graphics hardware via the virtual connection.

7830390, Nov 9, 2010

Jul 19, 2005

11/183848

David Shreiner - Mountain View CA, US

Graphics Properties Holdings, Inc. - Palo Alto CA

G06F 15/80
G06F 15/16

345505, 345502

A plurality of vertex or fragment processors on a graphics processor perform computations. Each vertex or fragment processor is capable of executing a separate program to compute a specific result. A combiner manages the combination of the results from the respective processors, and produces a final transformed vertex or pixel value. The vertex or fragment processors and the combiner can be programmable to modify their operations. As such, the vertex or fragment processors can operate in a parallel or serial configuration, or both. The combiner manages and resolves the operations of the serial and/or parallel configurations. A synchronization barrier enables the combiner to perform data-dependency analysis to determine the timing and ordering of the respective processors' execution. A transformation module can include one or more programmable vertex processors that transforms three-dimensional geometric data into fragments. The fragment processors subsequently receive and compute a result for each fragment, which is combined using the combiner to produce the final pixel value.

8194083, Jun 5, 2012

Nov 8, 2010

12/941423

David Shreiner - Mountain View CA, US

Graphics Properties Holdings, Inc. - Newark CA

G06F 15/80
G06F 15/16

345505, 345502

A plurality of vertex or fragment processors on a graphics processor perform computations. Each vertex or fragment processor is capable of executing a separate program to compute a specific result. A combiner manages the combination of the results from the respective processors, and produces a final transformed vertex or pixel value. The vertex or fragment processors and the combiner can be programmable to modify their operations. As such, the vertex or fragment processors can operate in a parallel or serial configuration, or both. The combiner manages and resolves the operations of the serial and/or parallel configurations. A synchronization barrier enables the combiner to perform data-dependency analysis to determine the timing and ordering of the respective processors' execution. A transformation module can include one or more programmable vertex processors that transforms three-dimensional geometric data into fragments. The fragment processors subsequently receive and compute a result for each fragment, which is combined using the combiner to produce the final pixel value.

8339409, Dec 25, 2012

Feb 16, 2011

12/929807

David Robert Shreiner - Mountain View CA, US

ARM Limited - Cambridge

G06T 15/30
G06T 1/20
G06F 15/16
G09G 5/36
G09G 5/00
G06K 9/36
G06K 9/54
G06K 9/60

345581, 345423, 345606, 345502, 345506, 345545, 382276, 382304, 382305, 382307

A tile-based graphics system, and method of operation of such a system, are provided for generating graphics data for a frame comprising a plurality of tiles. Graphics processing circuitry is provided which is arranged to be switched between a first mode of operation and a second mode of operation. In the first mode of operation, the graphics processing circuitry receives the plurality of graphics primitives for the frame, and performs a binning operation to determine, for each of the plurality of tiles, a tile list identifying the graphics primitives which intersect that tile. In the second mode of operation, the graphics processing circuitry receives the tile list for an allocated tile, and performs a rasterization operation to generate the graphics data for the allocated tile dependent on the tile list. This enables the same graphics processing unit to be used for both binning and rasterization operations, significantly reducing the size of the graphics system, while also allowing improvements in performance and energy consumption.

20060093044, May 4, 2006

Aug 24, 2005

11/209765

Brad Grantham - San Jose CA, US
David Shreiner - Mountain View CA, US
Alan Commike - San Jose CA, US

H04N 7/04

375240280, 386096000

A system and method for distributing data (e.g., imaging data such as pixels, or 3D graphics data such as points, lines, or polygons) from a single or a small number of data sources to a plurality of graphical processing units (graphics processors) for processing and display is presented. The system and method provide a pipelined and multithreaded approach that prioritizes movement of the data through a high-speed multiprocessor system (or a high-speed system of networked computers), according to the system topology. Multiple threads running on multiple processors in shared memory move the data from a storage device (e.g., a disk array), through the high-speed multiprocessor system, to graphics processor memory for display and optional processing through fragment programming. The data can also be moved in the reverse direction, back through the high-speed multiprocessor system, for storage on the disk array.

20110148892, Jun 23, 2011

Dec 17, 2009

12/654385

David Robert Shreiner - Mountain View CA, US
Ian Victor Devereux - Cambridge, GB
Edvard Sørgård - Hundhamaren, NO
Thomas Jeremy Olson - San Jose CA, US

ARM Limited - Cambridge

G09G 5/36

345545

A windowing display using deferred drawing commands operates by processing the drawing commands that write to a tile of a frame buffer to form one or more new pixel values are stored within a tile memory . Dirty pixel data indicative of which pixels within the tile memory are dirty pixels storing new pixel values and which pixels within the tile memory are clean pixels not storing new pixel values is also formed. In dependence upon the dirty pixel data, the new pixel value stored within the tile memory are written to the frame buffer memory. Pixels stored within the frame buffer memory corresponding to clean pixels within the tile memory remain unaltered as they are not written.

20140022264, Jan 23, 2014

Jul 18, 2012

13/552090

David Robert SHREINER - San Jose CA, US

ARM LIMITED - Cambridge

G06T 17/20

345520

A graphics processing unit having a shader execution unit for executing a plurality of shader routines in order to perform a predetermined sequence of shader operations. The shader operations include a tessellation operation which receives as inputs tessellation control data and an input list of input data for M input vertices, and generates at least output data for P output vertices. For each output vertex, the controller allocates a tessellation shader routine from the set of shader routines, and the shader execution unit is configured, each time the tessellation shader routine is executed for an associated output vertex: (i) to compute, in dependence on the tessellation control data and the associated output vertex, tessellation coordinate data; and (ii) to compute from the input data for the M input vertices, and the tessellation coordinate data generated in step (i), the output data for the associated output vertex.

20180089890, Mar 29, 2018

Sep 23, 2016

15/275152

- Cupertino CA, US
David R. Shreiner - Mountain View CA, US

G06T 15/80
G06T 17/20
G06T 7/00

Systems, methods, and computer readable media to implement tessellation edge shaders. Various embodiments receive tessellation patch information that includes patch information and shared edges for the patches. Based on the received patch information, edge tessellation levels for the shared edges may be determined and used to modify edge tessellation levels initially computed for the shared edges. The various embodiments can then generate vertices for a shared edge with the updated edge tessellation levels to adjoin the shared edges without forming cracks. The vertices may be used to render a surface of an object within a digital image or a sequence of digital images.