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David L Puziol

from Sunnyvale, CA
Age ~65
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Also known as:
David Louis Puziol, Dave L Puziol
Phone and address:
857 Helena Dr, Sunnyvale, CA 94087
(408) 749-1572
Related to:
Mervyn E FordAlexander J Puziol, 33Katherine Puziol, 31
Connected to:
Carmine R Puzo, 96Tina M Puzo, 58Elbert R Puzon, 52Karen O Puzon, 53Stacy A Puzon, 53Marcell Puzsar, 47Ashley M Puzycki, 33Dianne E Puzycki, 90John W Puzyk, 40Marcia G Puzzanghera, 67

David Puziol Phones & Addresses

  • 857 Helena Dr, Sunnyvale, CA 94087 (408) 749-1572 (408) 838-3958
  • Liverpool, NY
  • 857 Helena Dr, Sunnyvale, CA 94087 (408) 569-2658

Work

Company: Ericsson Jan 2007 to Jun 2014 Position: Principal asic design engineer

Education

Degree: Master of Science, Masters School / High School: Syracuse University Specialities: Electrical Engineering

Emails

d***[email protected]

Industries

Computer Networking

Resumes

Resumes

David Puziol Photo 1

David Puziol

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Location:
Sunnyvale, CA
Industry:
Computer Networking
Work:
Ericsson Jan 2007 - Jun 2014
Principal Asic Design Engineer
Redback Networks Mar 2000 - Jan 2007
Asic Design Engineer V
Siara Systems Jul 1998 - Mar 2000
Senior Member of Technical Staff
Fiberlane Communications Aug 1997 - Jul 1998
Senior Member of Technical Staff
Amd Jan 1996 - Aug 1997
Senior Member of Technical Staff
Education:
Syracuse University
Master of Science, Masters, Electrical Engineering University of Michigan
Bachelors, Bachelor of Science, Electrical Engineering

Publications

Us Patents

Configurable Branch Prediction For A Processor Performing Speculative Execution

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US Patent:
6360318, Mar 19, 2002
Filed:
Jun 29, 2000
Appl. No.:
09/608451
Inventors:
David L. Puziol - Sunnyvale CA
Korbin S. Van Dyke - Fremont CA
Larry Widigen - Salinas CA
Len Shar - Menlo Park CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 938
US Classification:
712240
Abstract:
In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically In software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.

Configurable Branch Prediction For A Processor Performing Speculative Execution

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US Patent:
6671798, Dec 30, 2003
Filed:
Nov 16, 2001
Appl. No.:
09/992822
Inventors:
David L. Puziol - Sunnyvale CA
Korbin S. Van Dyke - Fremont CA
Larry Widigen - Salinas CA
Len Shar - Menlo Park CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 938
US Classification:
712234
Abstract:
In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.

Pipeline Throughput Via Parallel Out-Of-Order Execution Of Adds And Moves In A Supplemental Integer Execution Unit

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US Patent:
58023399, Sep 1, 1998
Filed:
Feb 14, 1997
Appl. No.:
8/801709
Inventors:
Elliot A. Sowadsky - Santa Clara CA
Larry Widigen - Salinas CA
David L. Puziol - Sunnyvale CA
Korbin S. Van Dyke - Fremont CA
Assignee:
Advanced Micro Devices - Sunnyvale CA
International Classification:
G06F 930
G06F 938
US Classification:
395393
Abstract:
The existing execution units of a high-performance processor are augmented by the addition of a supplemental integer execution unit, termed the Add/Move Unit (AMU), which performs select adds and moves in parallel and out-of-order with respect to the other execution units. At small incremental cost, AMU enables better use of the expensive limited resources of an existing Address Preparation unit (AP), which handles linear and physical address generation for memory operand references, control transfers, and page crosses. AMU removes data dependencies and thereby increases the available instruction level parallelism. The increased instruction level parallelism is readily exploited by the processor's ability to perform out-of-order and speculative execution, and performance is enhanced as a result.

Processor Having Primary Integer Execution Unit And Supplemental Integer Execution Unit For Performing Out-Of-Order Add And Move Operations

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US Patent:
56757581, Oct 7, 1997
Filed:
Nov 15, 1994
Appl. No.:
8/340183
Inventors:
Elliot A. Sowadsky - Santa Clara CA
Larry Widigen - Salinas CA
David L. Puziol - Sunnyvale CA
Korbin S. Van Dyke - Fremont CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 938
US Classification:
395392
Abstract:
The existing execution units of a high-performance processor are augmented by the addition of a supplemental integer execution unit, termed the Add/Move Unit (AMU), which performs select adds and moves in parallel and out-of-order with respect to the other execution units. At small incremental cost, AMU enables better use of the expensive limited resources of an existing Address Preparation unit (AP), which handles linear and physical address generation for memory operand references, control transfers, and page crosses. AMU removes data dependencies and thereby increases the available instruction level parallelism. The increased instruction level parallelism is readily exploited by the processor's ability to perform out-of-order and speculative execution, and performance is enhanced as a result.

Configurable Branch Prediction For A Processor Performing Speculative Execution

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US Patent:
62826395, Aug 28, 2001
Filed:
Jun 29, 2000
Appl. No.:
9/608448
Inventors:
David L. Puziol - Sunnyvale CA
Korbin S. Van Dyke - Fremont CA
Larry Widigen - Salinas CA
Len Shar - Menlo Park CA
Walstein Bennett Smith - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 900
US Classification:
712240
Abstract:
In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.

Configurable Branch Prediction For A Processor Performing Speculative Execution

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US Patent:
58156992, Sep 29, 1998
Filed:
Jun 6, 1995
Appl. No.:
8/472698
Inventors:
David L. Puziol - Sunnyvale CA
Korbin S. Van Dyke - Fremont CA
Larry Widigen - Salinas CA
Len Shar - Menlo Park CA
Walstein Bennett Smith - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Austin TX
International Classification:
G06F 900
US Classification:
395586
Abstract:
In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.

Superscalar Execution Unit For Sequential Instruction Pointer Updates And Segment Limit Checks

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US Patent:
55903517, Dec 31, 1996
Filed:
Jan 21, 1994
Appl. No.:
8/185488
Inventors:
Elliot A. Sowadsky - Santa Clara CA
Larry Widigen - Salinas CA
David L. Puziol - Sunnyvale CA
Korbin S. Van Dyke - Fremont CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 938
US Classification:
395800
Abstract:
An execution unit performs multiple sequential instruction pointer updates and segment limit checks within a cycle. The updates and checks are carried out in a high-performance pipelined processor that speculatively executes variable length instructions. A disclosed embodiment of the execution unit includes Next EIP (Extended Instruction Pointer) selection logic, Current EIP selection logic, an EIP History RAM, a Dual EIP Adder, a CS Limit check adder, limit checking combinational logic, and a limit fault History RAM.

Branch Prediction Cache With Multiple Entries For Returns Having Multiple Callers

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US Patent:
56236140, Apr 22, 1997
Filed:
Sep 17, 1993
Appl. No.:
8/122922
Inventors:
Korbin S. Van Dyke - Fremont CA
Larry Widigen - Salinas CA
David L. Puziol - Sunnyvale CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 942
US Classification:
395587
Abstract:
A Branch Prediction Cache (BPC) selects from among multiple branch address entries for a single return-type instruction that returns to multiple callers. The BPC has a branch address associative memory, a return address associative memory, and word line logic used to validate and qualify entries. The branch address associative memory monitors program addresses for previously stored branch addresses. The return address stack (RtnStack) stores the return addresses for the most recent call-type instructions. The top of the stack is input to the return address associative memory. When a program address has multiple matches in the branch address associative memory, the return address associative memory enables only the entry that has an associated return address matching the top of the RtnStack. In an alternate embodiment, the return address associative memory is combined with a branch address cache and target address associative memory.
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David L Puziol from Sunnyvale, CA, age ~65 Get Report