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David J Palframan

from Austin, TX
Age ~38
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Connected to:
Douglas N Palfrey, 69Judith L Palfrey, 75Julia E Palfreyman, 104Morgan R Palfreyman, 46Ronald S Palfrey, 87Ryan A Palfrey, 43Sarah M Palfrey, 27Christopher J Palfy, 59Donna M Palfy, 67George P Palfy, 34

David Palframan Phones & Addresses

  • 8515 Brodie Ln APT 1332, Austin, TX 78745
  • Raleigh, NC
  • Madison, WI
  • Santa Clara, CA

Work

Company: Amd Mar 2019 Position: Member of technical staff

Education

Degree: Doctorates, Masters, Doctor of Philosophy School / High School: University of Wisconsin - Madison 2009 to 2015 Specialities: Computer Engineering, Philosophy

Skills

Computer Architecture • Verilog • Processors • Matlab • Simulations • Fpga • Xilinx • Vlsi • Functional Verification • C++ • Embedded Systems • Perl • Research • Latex

Languages

English • French

Industries

Computer Hardware

Resumes

Resumes

David Palframan Photo 1

Member Of Technical Staff

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Location:
Austin, TX
Industry:
Computer Hardware
Work:
Amd
Member of Technical Staff
Qualcomm
Senior Engineer
Arm Jul 2015 - Oct 2016
Senior Research Engineer
Qualcomm May 2013 - Aug 2013
Cpu R and D Intern
Ibm May 2012 - Apr 2013
Performance and Energy Modeling Intern
Education:
University of Wisconsin - Madison 2009 - 2015
Doctorates, Masters, Doctor of Philosophy, Computer Engineering, Philosophy Bucknell University 2005 - 2009
Bachelors, Electrical Engineering
Skills:
Computer Architecture
Verilog
Processors
Matlab
Simulations
Fpga
Xilinx
Vlsi
Functional Verification
C++
Embedded Systems
Perl
Research
Latex
Languages:
English
French

Publications

Us Patents

Systems And Devices For Compressing Neural Network Parameters

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US Patent:
20180373975, Dec 27, 2018
Filed:
Jun 21, 2017
Appl. No.:
15/629560
Inventors:
- Cambridge, GB
- Ann Arbor MI, US
David Palframan - Austin TX, US
Ganesh Dasika - Austin TX, US
Scott Mahlke - Ann Arbor MI, US
International Classification:
G06N 3/04
G06N 3/08
Abstract:
Subject matter disclosed herein may relate to storage and/or processing of signals and/or states representative of neural network parameters in a computing device, and may relate more particularly to compressing signals and/or states representative of neural network nodes in a computing device.

Systems And Devices For Formatting Neural Network Parameters

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US Patent:
20180373978, Dec 27, 2018
Filed:
Jun 21, 2017
Appl. No.:
15/629394
Inventors:
- Cambridge, GB
- Ann Arbor MI, US
David Palframan - Austin TX, US
Ganesh Dasika - Austin TX, US
Scott Mahlke - Ann Arbor MI, US
International Classification:
G06N 3/08
G06F 17/11
Abstract:
Subject matter disclosed herein may relate to storage of signals and/or states representative of parameters in a computing device, and may relate more particularly to storage of signals and/or states representative of neural network parameters in a computing device.

Adaptive Cache Prefetching Based On Competing Dedicated Prefetch Policies In Dedicated Cache Sets To Reduce Cache Pollution

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US Patent:
20150286571, Oct 8, 2015
Filed:
Apr 4, 2014
Appl. No.:
14/245356
Inventors:
- San Diego CA, US
David John Palframan - Madison WI, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 12/08
G06F 12/12
Abstract:
Adaptive cache prefetching based on competing dedicated prefetch policies in dedicated cache sets to reduce cache pollution is disclosed. In one aspect, an adaptive cache prefetch circuit is provided for prefetching data into a cache. The adaptive cache prefetch circuit is configured to determine which prefetch policy to use as a replacement policy based on competing dedicated prefetch policies applied to dedicated cache sets in the cache. Each dedicated cache set has an associated dedicated prefetch policy used as a replacement policy for the given dedicated cache set. Cache misses for accesses to each of the dedicated cache sets are tracked by the adaptive cache prefetch circuit. The adaptive cache prefetch circuit can be configured to apply a prefetch policy to the other follower (i.e., non-dedicated) cache sets in the cache using the dedicated prefetch policy that incurred fewer cache misses to its respective dedicated cache sets to reduce cache pollution.

Energy Efficient Optimization In Multicore Processors Under Quality Of Service (Qos)/Performance Constraints

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US Patent:
20150169032, Jun 18, 2015
Filed:
Dec 12, 2013
Appl. No.:
14/104154
Inventors:
- Armonk NY, US
Heather L. Hanson - Austin TX, US
David J. Palframan - Madison WI, US
Srinivasan Ramani - Cary NC, US
Ken V. Vu - Cary NC, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1/32
Abstract:
A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of sendee (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and die state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.

Energy Efficient Optimization In Multicore Processors Under Quality Of Service (Qos)/Performance Constraints

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US Patent:
20150169035, Jun 18, 2015
Filed:
Jun 13, 2014
Appl. No.:
14/304411
Inventors:
- Armonk NY, US
Heather L. Hanson - Austin TX, US
David J. Palframan - Madison WI, US
Srinivasan Ramani - Cary NC, US
Ken V. Vu - Cary NC, US
International Classification:
G06F 1/32
Abstract:
A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of service (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and the state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.
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David J Palframan from Austin, TX, age ~38 Get Report