David V Overhauser

6870255, Mar 22, 2005

Dec 15, 2000

09/739582

Steven Teig - Menlo Park CA, US
David Overhauser - Sunnyvale CA, US
Akira Fujimura - Saratoga CA, US

Cadence Design Systems, Inc. - San Jose CA

H01L023/12
G06L009/45

257700, 257758, 257773, 257776, 257786, 716 2, 716 5, 716 7, 716 8, 716 11, 716 12

An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections, such that a first section has a preferred direction and the second section has a preferred wiring direction that is different from the first preferred direction. The first and second preferred directions on a single metal layer may consist of any direction. The metal layer may be divided into more than two sections, wherein each section has a preferred wiring direction. Wiring geometries for multi-level metal layers are also disclosed.

6900540, May 31, 2005

Jan 11, 2002

10/043853

Steven Teig - Menlo Park CA, US
David Overhauser - Sunnyvale CA, US
Akira Fujimura - Saratoga CA, US

Cadence Design Systems, Inc. - San Jose CA

H01L023/48
H01L023/52
H01L029/40
G06F017/50

257758, 257700, 257701, 257208, 257211, 257207, 257203, 257 48, 257459, 257775, 257776, 257200, 257210, 257206, 364489, 364488, 716 2, 716 7, 716 1, 361735, 29850, 438197, 438 33, 438113

An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections, such that a first section has a preferred direction and the second section has a preferred wiring direction that is different from the first preferred direction. The first and second preferred directions on a single metal layer may consist of any direction. The metal layer may be divided into more than two sections, wherein each section has a preferred wiring direction. Wiring geometries for multi-level metal layers are also disclosed.

6987604, Jan 17, 2006

Feb 25, 2004

10/786665

Mario Rabinowitz - Redwood City CA, US
David Vincent Overhauser - Cupertino CA, US

G02B 26/00
G02B 7/182

359296, 359851, 359853, 359872, 359873

Due to an ever growing shortage of conventional energy sources, there is an increasingly intense interest in harnessing solar energy. The instant invention can contribute to the goal of achieving environmentally clean solar energy to be competitive with conventional energy sources. A novel method is described for manufacturing a transparent sheet with an embedded array of mirrored spheroidal micro-balls for use in a solar energy concentrator, and analogous applications such as optical switches and solar rocket assist. The micro-balls are covered with a thin spherical shell of lubricating liquid so that they are free to rotate in an almost frictionless encapsulation in the sheet. Novel method and apparatus are presented for producing the preferred embodiment of a close-packed monolayer of the array of mirrored micro-balls.

7653519, Jan 26, 2010

Apr 13, 2006

11/404636

David Overhauser - Cupertino CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 17/50

703 1, 716 4, 438 18

Disclosed are methods, systems, and structures for implementing interconnect modeling by using a test structure which include a variation of physical wire structures between local interconnects and distant interconnects. According to one approach, the impact of variations of the physical properties for neighborhood wires are considered for the electrical modeling of interconnects. This variation between the local and distant wire characteristics allows more accurate and robust interconnect modeling to be created.

7882464, Feb 1, 2011

Feb 13, 2006

11/354280

Steffen Rochel - Burlingame CA, US
David Overhauser - Cupertino CA, US
Gregory Steele - San Jose CA, US
Kung Hsu - Palo Alto CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 17/50

716 4, 716 5

Disclosed are systems and methods for electrical verification of integrated circuits. Methodologies are described for verification of the power and ground distribution systems (PDS) for system-on-a-chip (SoC) and the verification of the interaction of the PDS with the behavior of integrated circuits.

8316336, Nov 20, 2012

Dec 21, 2009

12/643813

David Overhauser - Cupertino CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 17/50
G06F 19/00
H03K 17/16
H03K 19/00
H01L 25/00
H01L 29/30
H01L 39/00
H01L 23/48
H01L 23/52

716122, 716123, 716129, 716130, 716136, 716111, 716 54, 716 55, 716 51, 326 31, 326 41, 326 47, 326101, 257618, 257662, 257663, 257758

Disclosed are methods, systems, and structures for implementing interconnect modeling by using a test structure which include a variation of physical wire structures between local interconnects and distant interconnects. According to one approach, the impact of variations of the physical properties for neighborhood wires are considered for the electrical modeling of interconnects. This variation between the local and distant wire characteristics allows more accurate and robust interconnect modeling to be created.

8365125, Jan 29, 2013

Jan 19, 2011

13/009817

Steffen Rochel - Burlingame CA, US
David Overhauser - Cupertino CA, US
Gregory Steele - San Jose CA, US
Kung Hsu - Palo Alto CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 17/50

716120, 716106, 716109, 716110, 716111, 716115, 716133, 716138

Disclosed are systems and methods for electrical verification of integrated circuits. Methodologies are described for verification of the power and ground distribution systems (PDS) for system-on-a-chip (SoC) and the verification of the interaction of the PDS with the behavior of integrated circuits.

8370778, Feb 5, 2013

Jan 19, 2011

13/009823

Steffen Rochel - Burlingame CA, US
David Overhauser - Cupertino CA, US
Gregory Steele - San Jose CA, US
Kung Hsu - Palo Alto CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 17/50

716106, 716109, 716111, 716115, 716120, 716133

Disclosed are systems and methods for electrical verification of integrated circuits. Methodologies are described for verification of the power and ground distribution systems (PDS) for system-on-a-chip (SoC) and the verification of the interaction of the PDS with the behavior of integrated circuits.