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David Nozadze

from San Jose, CA
Age ~37
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Connected to:
Akiko A Nozaki, 56Anna Nozaki, 47Daniel K Nozaki, 54Hiromichi Nozaki, 54Kenichi Nozaki, 73Masaki Nozaki, 74Michael Nozaki, 36Naomi F Nozaki, 88Jaleh Nozari, 89Nozar Nozarian, 46

David Nozadze Phones & Addresses

  • San Jose, CA
  • Rolla, MO
  • Columbus, OH

Resumes

Resumes

David Nozadze Photo 1

Senior Signal And Power Integrity Engineer

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Location:
San Francisco, CA
Industry:
Computer Networking
Work:
Cisco
Senior Signal and Power Integrity Engineer
Cisco Aug 2015 - Aug 2019
Signal and Power Integrity Engineer
Emc Lab at Missouri S&T Aug 2015 - May 2019
Graduate Research Assistant
Cisco Aug 2016 - Jan 2018
Signal Integrity Co-Op
The Ohio State University Aug 2013 - Aug 2015
Postdoctoral Researcher
Education:
Missouri University of Science and Technology 2015 - 2017
Master of Science, Masters, Electrical Engineering Missouri University of Science and Technology 2010 - 2013
Doctorates, Doctor of Philosophy, Physics, Philosophy I. Javakhishvili Tbilisi State University 2007 - 2009
Masters
Skills:
C++
Research
Statistics
Data Analysis
Python
Microsoft Office
Teaching
English
Machine Learning
Microsoft Excel
Powerpoint
Microsoft Word
Unix
Java
Matlab
Cst Microwave Studio
Agilent Ads
David Nozadze Photo 2

Operator

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Industry:
Oil & Energy
Work:
Bp
Operator
David Nozadze Photo 3

David Nozadze

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Skills:
Microsoft Office
Customer Service
Microsoft Excel
Leadership
Microsoft Word
Research
Powerpoint
Public Speaking
Social Media
Marketing

Publications

Us Patents

Integrated Circuit Package With Heatsink

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US Patent:
20220359366, Nov 10, 2022
Filed:
Sep 2, 2021
Appl. No.:
17/446729
Inventors:
- San Jose CA, US
Sayed Ashraf MAMUN - San Jose CA, US
Tomer OSI - Rosh Ahayin, IL
Amendra KOUL - San Francisco CA, US
David NOZADZE - San Jose CA, US
Upendranadh R. KARETI - Union City CA, US
Joel R. GOERGEN - Soulsbyville CA, US
International Classification:
H01L 23/50
H01L 23/367
H01L 23/498
Abstract:
An apparatus includes an integrated circuit package and a heatsink. The integrated circuit package includes a substrate, an integrated circuit, a first plurality of signal conductors, and a second plurality of signal conductors. The substrate includes a first surface and a second surface opposite the first surface. The integrated circuit is coupled to the first surface of the substrate. The first plurality of signal conductors are arranged along a periphery of the first surface of the substrate. The second plurality of signal conductors are arranged along a periphery of the second surface of the substrate. The heatsink includes a first portion positioned along the first surface of the substrate and a second portion positioned along the second surface of the substrate.

High Density Pinless Twinax Interconnect

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US Patent:
20220360005, Nov 10, 2022
Filed:
Mar 4, 2022
Appl. No.:
17/653466
Inventors:
- San Jose CA, US
Sayed Ashraf MAMUN - San Jose CA, US
Tomer OSI - Rosh Ahayin, IL
Amendra KOUL - San Francisco CA, US
David NOZADZE - San Jose CA, US
Upendranadh R. KARETI - Union City CA, US
Joel R. GOERGEN - Soulsbyville CA, US
International Classification:
H01R 12/72
H01R 12/75
Abstract:
Certain aspects of the present disclosure provide techniques for pinless interconnect for twinaxial cables to an IC. This includes a socket coupled to an integrated circuit (IC), a port structure coupled to the socket, and a ground connector inserted into the port structure. It further includes a twinaxial cable including a pair of conductors inserted through the ground connector to establish an electrical connection between the twinaxial cable and the IC.

Integrating Graphene Into The Skin Depth Region Of High Speed Communications Signals For A Printed Circuit Board

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US Patent:
20220217837, Jul 7, 2022
Filed:
Mar 24, 2022
Appl. No.:
17/703051
Inventors:
- San Jose CA, US
Scott Hinaga - Palo Alto CA, US
Jessica Kiefer - San Jose CA, US
Alpesh Umakant Bhobe - Sunnyvale CA, US
D. Brice Achkir - Livermore CA, US
David Nozadze - San Jose CA, US
Amendra Koul - San Francisco CA, US
Mehmet Onder Cap - Sunnyvale CA, US
Madeline Marie Roemer - Los Altos CA, US
International Classification:
H05K 1/02
Abstract:
A conductive signal transmission structure for an electronic device (e.g., a printed circuit board of an electronic device) includes a copper material and a graphene layer disposed within the copper material at a depth below a surface of the structure. The depth of the graphene layer is further within a skin depth region of the structure when a transmission signal applied to the conductive signal transmission structure has a signal speed of at least 112 Gbps.

Integrating Graphene Into The Skin Depth Region Of High Speed Communications Signals For A Printed Circuit Board

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US Patent:
20210337657, Oct 28, 2021
Filed:
Oct 26, 2020
Appl. No.:
17/079970
Inventors:
- San Jose CA, US
Scott Hinaga - Palo Alto CA, US
Jessica Kiefer - San Jose CA, US
Alpesh Umakant Bhobe - Sunnyvale CA, US
D. Brice Achkir - Livermore CA, US
David Nozadze - San Jose CA, US
Amendra Koul - San Francisco CA, US
Mehmet Onder Cap - Sunnyvale CA, US
Madeline Marie Roemer - Los Altos CA, US
International Classification:
H05K 1/02
Abstract:
A conductive signal transmission structure for an electronic device (e.g., a printed circuit board of an electronic device) includes a copper material and a graphene layer disposed within the copper material at a depth below a surface of the structure. The depth of the graphene layer is further within a skin depth region of the structure when a transmission signal is applied to the structure that is in the GHz frequency range.

Providing One Or More Carbon Layers To A Copper Conductive Material To Reduce Power Loss In A Power Plane

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US Patent:
20210337666, Oct 28, 2021
Filed:
Aug 28, 2020
Appl. No.:
17/006016
Inventors:
- San Jose CA, US
Jessica Kiefer - San Jose CA, US
Alpesh Umakant Bhobe - Sunnyvale CA, US
Kameron Rose Hurst - Sonora CA, US
D. Brice Achkir - Livermore CA, US
Amendra Koul - San Francisco CA, US
Scott Hinaga - Palo Alto CA, US
David Nozadze - San Jose CA, US
International Classification:
H05K 1/09
H05K 3/46
Abstract:
A power plane structure for a printed circuit board includes a copper layer, and a carbon layer applied directly to a surface of the copper layer. The carbon layer can include graphite or graphene. In additional embodiments, a duplicate power plane structure for a printed circuit board includes two power planes separated by an insulating core, each power plane including a copper layer and a carbon layer applied directly to a surface of the copper layer.

Optimizing Design And Performance For Printed Circuit Boards

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US Patent:
20210059055, Feb 25, 2021
Filed:
Aug 22, 2019
Appl. No.:
16/547639
Inventors:
- San Jose CA, US
Mike Sapozhnikov - San Jose CA, US
David Nozadze - San Jose CA, US
Joel Goergen - Soulsbyville CA, US
International Classification:
H05K 3/00
H05K 1/18
H05K 1/02
G06F 17/50
G01R 31/28
Abstract:
A printed circuit board (PCB) includes a plurality of layers disposed at different depths of the PCB, circuit components disposed at different layers of the PCB, and a plurality of temperature measurement sensors located at one or more layers of the PCB, where each temperature measurement sensor is associated with a corresponding circuit component. A measured temperature is obtained at an embedded temperature measurement sensor located at an embedded layer within the PCB, and the measured temperature is correlated with an electrical property of an embedded circuit component located at the same embedded layer within the PCB as the embedded temperature measurement sensor. A plurality of moisture measurement sensors can also be located at one or more layers of the PCB to facilitate a measured moisture with an electrical property of an embedded circuit component.
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David Nozadze from San Jose, CA, age ~37 Get Report