Search

David Hogenmiller Phones & Addresses

  • 9600 Bundoran Dr, Austin, TX 78717 (512) 925-4148
  • 6706 Fort Davis Cv, Austin, TX 78731
  • 12127 Cabana Ln, Austin, TX 78727
  • Round Rock, TX
  • 1804 Cattle Dr, Cedar Park, TX 78613 (512) 258-5411
  • Medford, NJ

Work

Company: Sun microsystems 2000 to Oct 2009 Position: Microprocessor circuit design enginner

Skills

Asic • Microprocessors • Circuit Design • Processors • Powerpc • Vlsi • Physical Design • Cmos • Semiconductors

Industries

Semiconductors

Resumes

Resumes

David Hogenmiller Photo 1

David Hogenmiller

View page
Location:
Austin, TX
Industry:
Semiconductors
Work:
Sun Microsystems 2000 - Oct 2009
Microprocessor Circuit Design Enginner

Ibm 1990 - 1999
Microprocessor Circuit Design Engineer
Skills:
Asic
Microprocessors
Circuit Design
Processors
Powerpc
Vlsi
Physical Design
Cmos
Semiconductors

Publications

Us Patents

Dividing And Distributing The Drive Strength Of A Single Clock Buffer

View page
US Patent:
6819138, Nov 16, 2004
Filed:
Nov 4, 2002
Appl. No.:
10/288407
Inventors:
David Hogenmiller - Cedar Park TX
Harsh Sharma - Austin TX
Shervin Hojat - Austin TX
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
H03K 190175
US Classification:
326 82, 326 31, 327293
Abstract:
Devices, methods, and networks that divide and proportionally distribute the drive strength of a clock buffer such that the output drive strength of the clock buffer is divided proportionally among a plurality of outputs from the clock buffer. In one embodiment, the present invention selectively couples adjacent parallel inverters present in a clock buffer to separate, internal distribution wires. The internal distribution wires are selectively coupled to one or more outputs by a connector wire to provide proportional, multiple outputs of the drive strength from the clock buffer to a clock network.

Use Of Coupling Capacitance To Balance Skew In A Network

View page
US Patent:
20040068709, Apr 8, 2004
Filed:
Oct 8, 2002
Appl. No.:
10/267336
Inventors:
Shervin Hojat - Austin TX, US
David Hogenmiller - Cedar Park TX, US
Harsh Sharma - Austin TX, US
Assignee:
Sun Microsystems, Inc.
International Classification:
G06F009/45
G06F017/50
US Classification:
716/010000
Abstract:
Coupling capacitance is used to balance skew in a network. In one embodiment, the coupling capacitance exerted by shielding wires oppositely adjacent one or more signal wires in a network is utilized to vary the speed of a signal carried on the one or more signal wires to balance skew in the network.

Template Based Clock Routing And Balancing

View page
US Patent:
20040078773, Apr 22, 2004
Filed:
Oct 21, 2002
Appl. No.:
10/277267
Inventors:
Harsh Sharma - Austin TX, US
Shervin Hojat - Austin TX, US
David Hogenmiller - Cedar Park TX, US
Assignee:
Sun Microsystems, Inc.
International Classification:
G06F017/50
US Classification:
716/013000, 716/014000
Abstract:
Predetermined and standardized path templates are introduced between points and/or elements in an integrated circuit layout. According to one embodiment of the invention, the standardized path templates are made up of two or more parallel tracks of path segments, with or without corresponding perpendicular path segments. According to the invention, the path segments are connected as needed to form serpentine or non-serpentine paths of the required length.
David G Hogenmiller from Austin, TX, age ~58 Get Report