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David Chudnovsky

from Brooklyn, NY
Age ~31
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Related to:
Sofiya Chudnovskiy, 37Sofiya Chudnovskiy, 94Simon Chudnovskiy, 71
Connected to:
Donald B Chudnow, 75Frank D Chudnow, 71James Chudnow, 80Marley Chudnow, 38Pavel E Chudnovsky, 65Andrea Chudoba, 58Brandi L Chudoba, 45David T Chudoba, 71Marek Chudoba, 49Mindy R Chudoba, 44

David Chudnovsky Phones & Addresses

  • 1660 W 2Nd St #1, Brooklyn, NY 11223

Resumes

Resumes

David Chudnovsky Photo 1

Professor

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Location:
Brooklyn, NY
Industry:
Higher Education
Work:
Nyu Tandon School of Engineering
Professor
David Chudnovsky Photo 2

David Chudnovsky

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Location:
Brooklyn, NY
Work:
Horizon Client Access May 2015 - Aug 2015
Intern
Education:
Allegheny College 2012 - 2016
Bachelors, Political Science and Government, Political Science, Government
Skills:
Microsoft Office
Microsoft Excel
Microsoft Word
Research
Powerpoint
Leadership

Publications

Wikipedia References

David Chudnovsky Photo 3

David Chudnovsky (Politician)

Us Patents

Multi-Bank, Fault-Tolerant, High-Performance Memory Addressing System And Method

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US Patent:
6519673, Feb 11, 2003
Filed:
Mar 26, 2002
Appl. No.:
10/107079
Inventors:
Gregory V. Chudnovsky - Forest Hills NY, 11375
David V. Chudnovsky - New York NY, 10025
International Classification:
G06F 1200
US Classification:
711 5, 711202, 711203, 711217
Abstract:
A memory addressing system for a multi-bank device that generally provides no band conflicts for stride data access patterns and infrequent bank conflicts for power of 2 stride patterns or other access patterns of interest. In a preferred embodiment, the device comprises an address translation or remapping unit that remaps sequences of logical addresses into sequences of slightly aperiodic physical addresses such that the physical addresses do not form a repetitive pattern of period less than N+1, where N is the number of memory banks, and do not on average repeat a physical bank number within approximately N physical addresses. In large memory modules and embedded logic devices wherein multiple memory units communicate with multiple microprocessors in a single chip, the disclosed remapping combined with disclosed scrambling methods also achieves high tolerance of chip defects which would otherwise render chips unusable, thereby yielding manufacturing economies.

Multi-Bank, Fault-Tolerant, High-Performance Memory Addressing System And Method

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US Patent:
6748480, Jun 8, 2004
Filed:
Oct 14, 2002
Appl. No.:
10/269890
Inventors:
Gregory V. Chudnovsky - Forest Hills NY, 11375
David V. Chudnovsky - New York NY, 10025
International Classification:
G06F 1200
US Classification:
711 5, 711202, 711203, 711217
Abstract:
A memory addressing system for a multi-bank memory device that generally provides no bank conflicts for stride 1 data access patterns and infrequent bank conflicts for power of 2 stride patterns or other access patterns of interest. In a preferred embodiment, the device comprises an address translation or remapping unit that remaps sequences of logical addresses into sequences of slightly aperiodic physical addresses such that the physical addresses do not form a repetitive pattern of period less than N+1, where N is the number of memory banks, and do not on average repeat a physical bank number within approximately N physical addresses. In large memory modules and embedded logic devices wherein multiple memory units communicate with multiple microprocessors in a single chip, the disclosed remapping combined with disclosed scrambling methods also achieves high tolerance of chip defects which would otherwise render chips unusable, thereby yielding manufacturing economies.

Method To Resolve An Incorrectly Entered Uniform Resource Locator (Url)

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US Patent:
7376752, May 20, 2008
Filed:
Oct 28, 2003
Appl. No.:
10/696240
Inventors:
David V. Chudnovsky - New York NY, US
Gregory V. Chudnovsky - Forest Hills NY, US
International Classification:
G06F 15/16
US Classification:
709245, 709217, 709219
Abstract:
A method and a carrier medium carrying code segments to cause a processor to implement a method for resolving a possibly incorrectly entered URL. The method includes accepting the entered URL, parsing the accepted URL into URL parts, and carrying out a conventional URL lookup. In one embodiment, for any part of the accepted URL that is not valid, the method includes determining a signature for the accepted URL part; and conducting a fuzzy search for at least one valid URL part that is close to the invalid URL part according to a distance measure that combines at least one local measure, each measure suited for a particular type of URL part. At least one valid URL may be formed from the URL parts found in the fuzzy search. In one implementation, the conducting of the fuzzy search includes: determining at least one cluster of a set of pre-formed clusters wherein the accepted URL part is likely to be. Each cluster includes a set of valid URL parts that are close according to a distance measure, and has a representative URL part having a known signature.

Multi-Bank, Fault-Tolerant, High-Performance Memory Addressing System And Method

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US Patent:
6381669, Apr 30, 2002
Filed:
Dec 27, 1999
Appl. No.:
09/472930
Inventors:
Gregory V. Chudnovsky - Forest Hills NY, 11375
David V. Chudnovsky - New York NY, 10025
International Classification:
G06F 1206
US Classification:
711 5, 711202, 711203, 711217
Abstract:
A memory addressing system for a multi-bank memory device that generally provides no bank conflicts for stride 1 data access patterns and infrequent ban conflicts for power of 2 stride patterns or other access patterns of interest. In a preferred embodiment, the device comprises an address translation or remapping unit that remaps sequences of logical addresses into sequences of slightly aperiodic physical addresses such that the physical addresses do not form a repetitive pattern of period less than N+1, where N is the number of memory banks, and do not on average repeat a physical bank number within approximately N physical addresses. In large memory modules and embedded logic devices wherein multiple memory units communicate with multiple microprocessors in a single chip, the disclosed remapping combined with disclosed scrambling methods also achieves high tolerance of chip defects which would otherwise render chips unusable, thereby yielding manufacturing economies.

Isbn (Books And Publications)

Additive Number Theory: Festschrift in Honor of the Sixtieth Birthday of Melvyn B. Nathanson

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Author

David Chudnovsky

ISBN #

0387370293

Classical and Quantum Models and Arithmetic Problems

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Author

David Chudnovsky

ISBN #

0824718259

Search Theory: Some Recent Developments

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Author

David V. Chudnovsky

ISBN #

0824780000

Computer Algebra

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Author

David V. Chudnovsky

ISBN #

0824780388

Computers in Mathematics

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Author

David V. Chudnovsky

ISBN #

0824783417

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David Chudnovsky from Brooklyn, NY, age ~31 Get Report