Darren J Walworth

8367469, Feb 5, 2013

Jan 10, 2012

13/347543

Andrew J. Bonthron - Los Angeles CA, US
Darren Jay Walworth - Fullerton CA, US

Semtech Corporation - Camarillo CA

H01L 21/00

438107, 438108, 438122, 257713, 257724, 257704, 257E23101, 257E2319, 257E215, 257E21511

A method of packaging one or more semiconductor dies is provided. The method includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame using a third coupling mechanism.

8487430, Jul 16, 2013

Jan 21, 2010

12/691675

Darren Jay Walworth - Fullerton CA, US

Semtech Corporation - Camarillo CA

H01L 23/64

257728, 257698, 257664, 257700, 257E2301

Examples of high-speed ball grid array packages and a process of forming a package are provided. A package may include contact pads disposed on a bottom surface, conductive balls, and a signal via structure. The package may also include a first ground via structure arranged along one or more first semi-circular contours around the signal via structure and extending vertically and a second ground via structure arranged along one or more second semi-circular contours around the signal via structure and extending vertically. The package may include a ground interface plane disposed in separation from the signal contact pad by a distance. The distance may be determined based on at least a size of the signal contact pad, a dielectric constant of a transition layer between the ground interface plane and the signal contact pad, and a distance between the signal via structure and the second ground via structure.

20110140260, Jun 16, 2011

Dec 10, 2009

12/635677

Andrew J. Bonthron - Los Angeles CA, US
Darren Jay Walworth - Fullerton CA, US

SIERRA MONOLITHICS, INC. - Redondo Beach CA

H01L 23/488
H01L 23/34
H01L 23/04
H01L 21/60
H01L 21/50

257690, 257712, 257704, 438108, 438122, 257E2308, 257E23181, 257E23023, 257E21511, 257E21499

A chip assembly may comprise a substrate having a top surface and a bottom surface. The chip assembly may comprise a first die having a circuit surface and a connecting surface, the circuit surface comprising one or more integrated circuits. The chip assembly may comprise a chip-scale frame having an inside surface, an outside surface, and a well region, the well region having an opening within the inside surface, the well region having a wall, the well region housing the first die, the first die attached to the wall by a first coupling mechanism, the inside surface coupled to the top surface of the substrate by a second coupling mechanism. The chip assembly may comprise a heat sink coupled to the outside surface of the chip-scale frame using a third coupling mechanism.

20130130441, May 23, 2013

Jan 15, 2013

13/742252

Darren Jay WALWORTH - Fullerton CA, US

SEMTECH CORPORATION - Camarillo CA

H01L 21/50

438107

A method of packaging one or more semiconductor dies includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame; attaching a lid to the chip-scale frame to form a substantially airtight chamber around the first die.