Darren M Bertanzetti

7895488, Feb 22, 2011

Jun 19, 2007

11/765275

Darren Bertanzetti - Thornton CO, US

Marvell International Ltd. - Hamilton

G01R 31/28
G01R 31/02
G01R 31/26
G06F 11/00

714728, 714 25, 714 30, 714724, 714726, 714729, 714731, 714739, 324537, 324763, 324765

A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be present.

8024631, Sep 20, 2011

Nov 6, 2007

11/982937

Darren Bertanzetti - Thornton CO, US

Marvell International Ltd. - Hamilton

G01R 31/28

714729

A scan test circuit includes a plurality of tester inputs that receive scan test data for performance of a scan test of a circuit under test. The scan test circuit also includes first and second sets of scan chains that include first and second sets of state variable devices, respectively. The first and second sets of scan chains communicate with the plurality of tester inputs. The scan test circuit also includes first and second compressors that receive a first clock signal and an inversion of the first clock signal, respectively. The compressors compress data output from the first and second sets of state variable devices, respectively. The compressors also generate first and second compressor output data, respectively, based on the compression. The scan test circuit also includes a plurality of tester outputs that provide output test data based on the first and second compressor output data.

8214704, Jul 3, 2012

Sep 16, 2011

13/235278

Darren Bertanzetti - Thornton CO, US

Marvell International Ltd. - Hamilton

G01R 31/28

714729, 714732

A system including a first clock, a first scan chain, and a first sampling circuit. The first clock is configured to generate a first clock signal. The first scan chain includes a first input, a first set of devices, and a first output. The first input is configured to receive a portion of first data to test the first scan chain. The first set of devices has a first plurality of states, wherein each of the first set of devices changes between the first plurality of states in response to the portion of the first data. The first output is configured to output a portion of second data in response to the first plurality of states. The first sampling circuit is configured to sample the portion of the second data from the first output at least twice per clock cycle of the first clock signal.

8443246, May 14, 2013

Jan 27, 2011

13/014921

Darren Bertanzetti - Broomfield CO, US

Marvell International Ltd. - Hamilton

G01R 31/28
G01R 31/02
G01R 31/26
G06F 11/00

714728, 714 25, 714 30, 714724, 714726, 714729, 714731, 714739, 324537, 32476201, 32476202, 32476203, 32476205

A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be present.

7739568, Jun 15, 2010

Nov 13, 2007

11/983856

Darren Bertanzetti - Thornton CO, US

Marvell International Ltd. - Hamilton

G01R 31/28
G11B 27/00

714729, 714731, 714814

A scan test circuit includes tester inputs that receive scan test data. Scan chains are coupled to the tester inputs. The tester outputs are coupled to the scan chains and provide output test data based on the scan test data. A first clock generates a first clock signal. A sampling circuit samples each of the tester outputs at least twice per clock cycle of the first clock signal.