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Darrell L Boggs

from Burlington, NC
Age ~49
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Also known as:
Darrell Lee Boggs
Phone and address:
233 Boone Rd, Burlington, NC 27217
Related to:
Wanda Brummett Biggs, 69Wanda B BiggsJoyce J Kirk, 67Kenneth D Boggs, 69C MannPamela W Boggs, 67Sylvia B Teague, 74James W Mann, 44Richard D Lamoreaux, 67Christina Juanita Boggs-Mann, 49Christina J Mann, 48Christopher B Lamoreaux, 38Christina J Mann, 48Jeremy K Boggs, 29
Connected to:
Alicia N Boggs, 46April K Boggs, 46Auston L Boggs, 37Betty A Boggs, 65Bonnie M Boggs, 74Breanna Boggs, 29Caleb Boggs, 33Calvin J Boggs, 35Carmen Boggs, 52Charyll M Boggs, 77

Darrell Boggs Phones & Addresses

  • 233 Boone Rd, Burlington, NC 27217
  • 420 First St, Mebane, NC 27302 (919) 563-2604
  • Snow Camp, NC
  • Graham, NC
  • 2200 195Th Ave, Aloha, OR 97006 (503) 591-8779
  • Beaverton, OR
  • Swepsonville, NC

Work

Position: Professional/Technical

Business Records

Name / Title
Company / Classification
Phones & Addresses
Darrell Boggs
Owner
Nizhoni Properties LLC
Nonresidential Building Operator
2200 SW 195 Ave, Beaverton, OR 97006
(503) 591-8779
Darrell D. Boggs
JAD DEVELOPMENT, LLC

Publications

Us Patents

Multi-Threading For A Processor Utilizing A Replay Queue

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US Patent:
6385715, May 7, 2002
Filed:
May 4, 2001
Appl. No.:
09/848423
Inventors:
Amit A. Merchant - Portland OR
Darrell D. Boggs - Aloha OR
David J. Sager - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1500
US Classification:
712219, 712 23, 712218, 709106
Abstract:
A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store long latency instruction for each thread until the long latency instruction is ready to be executed (e. g. , data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.

Processor Instruction Pipeline With Error Detection Scheme

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US Patent:
6457119, Sep 24, 2002
Filed:
Jul 23, 1999
Appl. No.:
09/360192
Inventors:
Darrell Boggs - Aloha OR
Robert F. Krick - Fort Collins CO
Chan Lee - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 938
US Classification:
712227, 712231
Abstract:
Briefly, in accordance with one embodiment of the invention, a processor includes: a multiple unit instruction pipeline. An instruction pipeline includes a microcode source. The microcode source includes the capability of detecting the occurrence of at least one corrupted microcode instruction. The microcode source is also capable of signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. Briefly, in accordance with another embodiment of the invention, a method of executing microcode instructions includes the following. The existence of at least one corrupted microcode instruction is detected and the occurrence of at least one corrupted microcode instruction is signaled. Briefly, in accordance with one more embodiment of the invention, a system includes: a processor with a microcode source capable of detecting the occurrence of at least one corrupted microcode instruction and signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. The system employing the processor further includes main memory, a video card, a system bus, and bulk storage capability.

Method And System For An Inuse Field Resource Management Scheme

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US Patent:
6467027, Oct 15, 2002
Filed:
Dec 30, 1999
Appl. No.:
09/475746
Inventors:
Alan B. Kyker - Portland OR
Darrell D. Boggs - Aloha OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1200
US Classification:
711125, 711141
Abstract:
A method for maintaining an instruction in a pipelined processor using inuse fields. The method involves receiving a read request for an instruction, sending the instruction in response to the read request and setting an inuse field associated with the instruction to inuse. Alternate embodiments of the method involve transmitting the instruction in response to the read request, receiving a notification of instruction retirement and resetting the inuse field in the ITLB. The method can also be used in the ICACHE in which inuse fields are associated with each instruction stored in the ICACHE. Other embodiments of the method can be used concurrently in the ITLB and the ICACHE as a resource tracking mechanism to maintain resources.

Method And Apparatus For Processing An Event Occurrence Within A Multithreaded Processor

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US Patent:
6496925, Dec 17, 2002
Filed:
Dec 9, 1999
Appl. No.:
09/458544
Inventors:
Dion Rodgers - Hillsboro OR
Darrell Boggs - Aloha OR
Amit Merchant - Portland OR
Rajesh Kota - Aloha OR
Rachel Hsu - Hillsboro OR
Keshavan Tiruvallur - Tigard OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 938
US Classification:
712244, 712216, 712218, 712 1, 710262
Abstract:
A method includes detecting a first event occurrence for a first thread being processed within a multithreaded processor. Responsive to the detection of this first event occurrence, a second thread being processed within the multithreaded processor is monitored to detect a clearing point for this second thread. Responsive to the detection of a clearing point for the second thread, a functional unit within the multithreaded processor is cleared of data for both the first and the second threads.

Method And System For An Inuse Field Resource Management Scheme

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US Patent:
6591344, Jul 8, 2003
Filed:
Aug 15, 2002
Appl. No.:
10/218628
Inventors:
Alan B. Kyker - Portland OR
Darrell D. Boggs - Aloha OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1200
US Classification:
711125, 711117, 711123, 711202, 711206, 711205, 712205, 712226
Abstract:
A method for maintaining an instruction in a pipelined processor using inuse fields. The method involves receiving a read request for an instruction, sending the instruction in response to the read request and setting an inuse field associated with the instruction to inuse. Alternate embodiments of the method involve transmitting the instruction in response to the read request, receiving a notification of instruction retirement and resetting the inuse field in the ITLB. The method can also be used in the ICACHE in which inuse fields are associated with each instruction stored in the ICACHE. Other embodiments of the method can be used concurrently in the ITLB and the ICACHE as a resource tracking mechanism to maintain resources.

Processor With Registers Storing Committed/Speculative Data And A Rat State History Recovery Mechanism With Retire Pointer

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US Patent:
6633970, Oct 14, 2003
Filed:
Dec 28, 1999
Appl. No.:
09/472840
Inventors:
David W. Clift - Hillsboro OR
Darrell D. Boggs - Aloha OR
David J. Sager - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 938
US Classification:
712217, 712 23, 712218
Abstract:
A mechanism is provided for allowing a processor to recover from a failure of a predicted path of instructions (e. g. , from a mispredicted branch or other event). The mechanism includes a plurality of physical registers, each physical register can store either architectural data or speculative data. The apparatus also includes a primary array to store a mapping from logical registers to physical registers, the primary array storing a speculative state of the processor. The apparatus also includes a buffer coupled to the primary array to store information identifying which physical registers store architectural data and which physical registers store speculative data. According to another embodiment, a history buffer is coupled to the secondary array and stores historical physical register to logical register mappings performed for each of a plurality of instructions part of a predicted path. The secondary array is movable to a particular speculative state based on the mappings stored in the history buffer, such as to a location where a path failure may occur. The secondary array can then be copied to the primary array when a failure is detected in a predicted path of instructions near where the secondary array is located to allow the processor to recover from the predicted path failure.

Determination Of Approaching Instruction Starvation Of Threads Based On A Plurality Of Conditions

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US Patent:
6651158, Nov 18, 2003
Filed:
Jun 22, 2001
Appl. No.:
09/888274
Inventors:
David W. Burns - Portland OR
James D. Allen - Portland OR
Michael D. Upton - Portland OR
Darrell D. Boggs - Aloha OR
Alan B. Kyker - Davis CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 946
US Classification:
712205, 709103
Abstract:
In a multi-threaded processor, thread priority variables are set up in memory. According to an embodiment of the present invention, several conditions are monitored so as to determine an indication of instruction side starvation may be approaching. If such starvation is approaching, the starvation is resolved upon the expiration of a threshold counter or the like.

Interface To A Memory System For A Processor Having A Replay System

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US Patent:
6665792, Dec 16, 2003
Filed:
Dec 30, 1999
Appl. No.:
09/475029
Inventors:
Amit A. Merchant - Portland OR
Darrell D. Boggs - Aloha OR
David J. Sager - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 900
US Classification:
712219, 712 32, 712225
Abstract:
A processor includes a memory execution unit for executing load and store instructions and a replay system for replaying instructions which have not executed properly. The memory execution unit including an invalid store flag that is set for a store instruction if the replay system detects that the store instruction has not executed properly and is cleared if the store instruction has executed properly. If an invalid store flag is set for a store instruction, the replay system replays load instructions which are programmatically younger than the invalid store instruction until the store instruction executes properly.
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Darrell L Boggs from Burlington, NC, age ~49 Get Report