Danny R Cline

6353563, Mar 5, 2002

Mar 15, 1999

09/268281

Kuong Hua Hii - Singapore, SG
Danny R. Cline - Dallas TX
Theo J. Powell - Dallas TX

Texas Instruments Incorporated - Dallas TX

G01R 3128

365201, 714 30, 714 37, 714 39, 714 25, 714 48, 714724, 714733, 714734, 371 223, 371 2201

An integrated circuit has a built-in self-test (BIST) arrangement ( ). The built-in self-test arrangement includes a read only memory (ROM), ( ) that stores test algorithm instructions. A ROM logic circuit ( ) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

6438718, Aug 20, 2002

Jun 15, 1994

08/259798

Danny R. Cline - Plano TX

Texas Instruments Incorporated - Dallas TX

G11C 2900

714718, 365201

An integrated circuit memory device includes a wordline stress mode arrangement and a storage cell initialization arrangement with the array of storage cells. In the wordline stress mode arrangement, a plurality of wordlines are run across the array. Each wordline is connected with the gates of transfer transistors of a different row of the storage cells. A decoder, responsive to a control signal, simultaneously applies a supply voltage to the wordlines. The supply voltage may be provided by a selectable magnitude external source. In the cell initialization arrangement, a plurality of complementary pairs of bitlines are run across the array. Each complementary pair of the bitlines interconnects with the storage cells in a separate column of the array. A precharge circuit is arranged for precharging the bitlines to a precharge voltage. a precharge disabling circuit, responsive to the control signal, disables the precharge circuit from applying the precharge voltage and supplies an alterntive voltage to the pairs of bitlines.

6801461, Oct 5, 2004

Dec 17, 2001

10/023308

Kuong Hua Hii - Singapore, SG
Danny R. Cline - Dallas TX
Theo J. Powell - Dallas TX

Texas Instruments Incorporated - Dallas TX

G11C 1100

365201, 714726, 714718, 714733

An integrated circuit has a built-in self-test (BIST) arrangement ( ). The built-in self-test arrangement includes a read only memory (ROM), ( ) that stores test algorithm instructions. A ROM logic circuit ( ) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

7278078, Oct 2, 2007

Aug 12, 2004

10/918813

Kuong Hua Hii - Singapore, SG
Danny R. Cline - Dallas TX, US
Theo J. Powell - Dallas TX, US

Texas Instruments Incorporated - Dallas TX

G01R 31/28
G06F 11/00
G11C 29/00

714733, 714734, 714718, 714706, 714763, 365201

An integrated circuit has a built-in self-test (BIST) arrangement (). The built-in self-test arrangement includes a read only memory (ROM), () that stores test algorithm instructions. A Rom logic circuit () receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

7328388, Feb 5, 2008

Jan 24, 2006

11/338029

Kuong Hua Hii - Singapore, SG
Danny R. Cline - Dallas TX, US
Theo J. Powell - Dallas TX, US

Texas Instruments Incorporated - Dallas TX

G06F 3/00
G06F 15/177

714733, 714736

An integrated circuit has a built-in self-test (BIST) arrangement (). The built-in self-test arrangement includes a read only memory (ROM), () that stores test algorithm instructions. A ROM logic circuit () receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

20020071325, Jun 13, 2002

Aug 28, 2001

09/941075

Kuong Hii - Singapore, SG
Danny Cline - Dallas TX, US
Theo Powell - Dallas TX, US

G11C029/00

365/201000

An integrated circuit has a built-in self-test (BIST) arrangement (). The built-in self-test arrangement includes a read only memory (ROM), () that stores test algorithm instructions. A ROM logic circuit () receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

59599120, Sep 28, 1999

Jan 9, 1998

9/005359

Theo J. Powell - Dallas TX
Kuong Hua Hii - Singapore, SG
Danny R. Cline - Plano TX
Wah Kit Loh - Richardson TX

Texas Instruments Incorporated - Dallas TX

G11C 700

365201

A read-only memory (ROM) embedded mask release number for a built-in self-test of a memory device is provided. A synchronous dynamic random access memory (10) comprises a conventional memory (12) and a built-in self-test arrangement (14). The built-in self-test arrangement (14) includes a read only memory (ROM) (72) which stores a plurality of algorithms. Each algorithm is comprised of a series of array access instructions (140) and program access instructions (142). The last instruction in ROM (72) is an idle instruction (120). Associated with idle instruction (120) is an identification number (132). Once stored in ROM (72), the identification number (132) can be read without the use of additional equipment.

57426147, Apr 21, 1998

Nov 25, 1996

8/756313

Danny R. Cline - Plano TX

Texas Instruments Incorporated - Dallas TX

G06F 1100

371 212

A semiconductor random access memory having a complex topology is provided with ROM unit storing every potential row data pattern to be entered in the storage cell array during a test procedure, a variable step address generator, a comparator mechanism, and a control unit. In response to signals from the control unit, the variable step address generator enters each row data pattern at appropriate addresses determined by the periodicity of the complex topography. The variable step address generator is then used to retrieve stored data groups from addresses used to store each ROM data pattern. The retrieved data groups are compared with the ROM data pattern used as a template for the stored data group. A record of the comparison errors can be stored in an erasable memory unit.