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Daniel L Falkoff

from Billerica, MA
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Also known as:
Dan Falkoff
Connected to:
Marc D Falkoff, 58Anthonie J Falkoski, 32Jamie Falkosky, 57Chaim Falkovits, 47Guy Falkovitch, 45Yakov Falkovich, 38Yan A Falkovsky, 49Michael D Falkow, 57Juda Falkowitz, 45Kenneth J Falkowitz, 61

Daniel Falkoff Phones & Addresses

  • Billerica, MA
  • Westford, MA
  • Longmeadow, MA
  • Palmer, MA

Resumes

Resumes

Daniel Falkoff Photo 1

Principal Compensation Analyst

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Location:
3 Ardsmoor Rd, Melrose, MA 02176
Industry:
Computer Software
Work:
Nuance Communications
Principal Compensation Analyst
Eastern Bank Oct 2016 - Jan 2018
Vice President Compensation Manager
Inventiv Health Jun 2014 - Sep 2016
Compensation Manager
Smith & Nephew May 2012 - Jun 2014
Senior Compensation Analyst
Willis Towers Watson Aug 2010 - May 2012
Consultant and Compensation Analyst
Education:
Suffolk University 2008
University of Massachusetts Amherst 2005
Bachelors, Bachelor of Arts, Psychology Suffolk University
Skills:
Executive Pay
Deferred Compensation
Human Resources
Incentive Programs
Talent Management
Compensation and Benefits
Salary
Compensation and Benefit
Job Evaluation
Hr Consulting
Performance Management
Employee Benefits
Job Analysis
Benefits Administration
Hr Policies
Organizational Design
Interests:
Human Rights
Science and Technology
Environment
Health
Languages:
English
Certifications:
Certified Compensation Professional
Daniel Falkoff Photo 2

Surgical Technologist At Umass Memorial Medical Center

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Location:
Greater Boston Area
Industry:
Hospital & Health Care
Daniel Falkoff Photo 3

Daniel Falkoff

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Daniel Falkoff Photo 4

Daniel Falkoff

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Publications

Us Patents

Digital Data Processor With High Reliability

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US Patent:
46548572, Mar 31, 1987
Filed:
Aug 2, 1985
Appl. No.:
6/762039
Inventors:
Joseph E. Samson - Dover MA
Kenneth T. Wolff - Medway MA
Robert Reid - Dunstable MA
Gardner C. Hendrie - Marlboro MA
Daniel M. Falkoff - Natick MA
Ronald E. Dynneson - Brighton MA
Daniel M. Clemson - Weston MA
Kurt F. Baty - Medway MA
Assignee:
Stratus Computer, Inc. - Marlboro MA
International Classification:
G06F 1120
US Classification:
371 68
Abstract:
A fualt-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units. Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit. The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

Digital Data Processor Apparatus With Pipelined Fault Tolerant Bus Protocol

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US Patent:
47501774, Jun 7, 1988
Filed:
Sep 8, 1986
Appl. No.:
6/904827
Inventors:
Gardner C. Hendrie - Marlboro MA
Kurt F. Baty - Medway MA
Ronald E. Dynneson - Brighton MA
Daniel M. Falkoff - Natick MA
Robert Reid - Dunstable MA
Joseph E. Samson - Dover MA
Kenneth T. Wolff - Medway MA
Assignee:
Stratus Computer, Inc. - Marlboro MA
International Classification:
G06F 1100
US Classification:
371 32
Abstract:
A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units. Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit. The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.
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Daniel L Falkoff from Billerica, MA Get Report