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Daniel J Cimino

from Las Vegas, NV
Age ~71

Daniel Cimino Phones & Addresses

  • 5508 Royal Vista Ln, Las Vegas, NV 89149
  • La Quinta, CA
  • 1855 Kirkmont Dr, San Jose, CA 95124 (408) 266-0565 (408) 266-4603
  • Campbell, CA
  • Berkeley, CA
  • Santa Clara, CA
  • Sunnyvale, CA
  • San Mateo, CA
  • 1855 Kirkmont Dr, San Jose, CA 95124 (408) 266-4603

Work

Position: Professional/Technical

Education

Degree: Associate degree or higher

Business Records

Name / Title
Company / Classification
Phones & Addresses
Daniel J. Cimino
President
MID-STATE ELECTRIC, INC
Electrical Contractor
1855 Kirkmont Dr, San Jose, CA 95124
(408) 374-9077

Publications

Us Patents

Protocol For Communicating Data Between Packet Forwarding Devices Via An Intermediate Network Interconnect Device

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US Patent:
59744677, Oct 26, 1999
Filed:
Feb 27, 1998
Appl. No.:
9/032803
Inventors:
Stephen R. Haddock - Los Gatos CA
Herb Schneider - San Jose CA
Daniel J. Cimino - Oak Park CA
Siddharth Khattar - Goleta CA
Matthew T. Knudstrup - Oak Park CA
Aaron C. Tyler - Thousand Oaks CA
Assignee:
Extreme Networks - Santa Clara CA
International Classification:
G06F 1314
H04L 1228
H04L 1246
US Classification:
709240
Abstract:
A message exchange protocol for interconnecting packet forwarding devices through an intermediate network interconnect device is provided. According to one aspect of the present invention, a method is provided for communicating data between packet forwarding devices. The presence of an interconnect device that is coupled between a first packet forwarding device and a second packet forwarding device is detected by recognizing a configuration sequence, for example. After the link between the interconnect device and the first packet forwarding device is established, the first packet forwarding device receives a command from the interconnect device requesting the types of data that are pending on the first packet forwarding device. Responsive to the command, the first packet forwarding device transmits a "menu" including information indicating the availability of one or more types of data that are awaiting transmission to the interconnect device. An "order" is received by the first packet forwarding device from the interconnect device.

Media Access Controller

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US Patent:
53792890, Jan 3, 1995
Filed:
Jul 16, 1993
Appl. No.:
8/093458
Inventors:
Edwin Z. DeSouza - San Jose CA
Daniel J. Cimino - Sunnyvale CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H04L 1246
H04J 326
US Classification:
370 8513
Abstract:
A media access controller is provided by the present invention. A feature of the media access controller of the present invention is a content addressable memory architecture whereby address filtering is provided for filtering physical, group and broadcast addresses on an Ethernet network. Another feature of the present invention is an interface architecture capable of supporting external address filters which in turn are capable of supporting spanning tree and source routing algorithms. Still another feature of the present invention is a CRC checker having improved testability such that burdensome computations for input bit test patterns are no longer required. Still another feature of the present invention is a first-in, first-out memory register having validity bits associated with each stored data byte, such that data bytes may be indiscriminately stored, regardless of their validity, and invalid data bytes are discarded during retrieval of the stored data bytes.

Cyclic Redundancy Check Circuit

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US Patent:
51649438, Nov 17, 1992
Filed:
Mar 6, 1992
Appl. No.:
7/847357
Inventors:
Edwin Z. DeSouza - San Jose CA
Daniel J. Cimino - Sunnyvale CA
Ramin Shirani - Morgan Hill CA
Mark R. Waggoner - Palo Alto CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G06F 1112
US Classification:
371 3
Abstract:
A media access controller is provided by the present invention. A feature of the media access controller of the present invention is a content addressable memory architecture whereby address filtering is provided for filtering physical, group and broadcast addresses on an Ethernet network. Another feature of the present invention is an interface architecture capable of supporting external address filters which in turn are capable of supporting spanning tree and source routing algorithms. Still another feature of the present invention is a CRC checker having improved testability such that burdensome computations for input bit test patterns are no longer required. Still another feature of the present invention is a first-in, first-out memory register having validity bits associated with each stored data byte, such that data bytes may be indiscriminately stored, regardless of their validity, and invalid data bytes are discarded during retrieval of the stored data bytes.

Hub Management Bus Architecture For Repeater Interface Controller

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US Patent:
53964950, Mar 7, 1995
Filed:
Jun 18, 1993
Appl. No.:
8/079210
Inventors:
Charles A. Moorwood - Sunnyvale CA
Charan J. Singh - Fairfield CA
Daniel J. Cimino - Mountain View CA
Howard Quoc Vo - San Jose CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H04J 326
H04L 1256
US Classification:
370 8511
Abstract:
The present invention is directed to various features of a repeater interface controller (RIC) that connects segments of a bus/tree local area network. In the described embodiment of the invention, the RIC implements the IEEE 802. 3 repeater specification. In accordance with another aspect of the present invention, the RIC provides hub management support in the form of information regarding the status of its ports and of the packets it is repeating. This data is available in three forms: counted events, recorded events and status packets. This information is available through the RIC's interface. The counters and event recording registers have user-definable masks which enable them to be configured to count and record a variety of events. In accordance with another aspect of the present invention, the RIC management statistics at maximum network bandwidth. Statistics are logged while a packet repetition is in process and are furnished to counter and flag arrays after transmission of the same packet has ended.

First-In, First-Out Memory Circuit

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US Patent:
52456170, Sep 14, 1993
Filed:
Mar 6, 1992
Appl. No.:
7/847952
Inventors:
Edwin Z. DeSouza - San Jose CA
Daniel J. Cimino - Sunnyvale CA
Ramin Shirani - Morgan Hill CA
Mark R. Waggoner - Palo Alto CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G06F 1110
US Classification:
371 371
Abstract:
A media access controller is provided by the present invention. A feature of the media access controller of the present invention is a content addressable memory architecture whereby address filtering is provided for filtering physical, group and broadcast addresses on an Ethernet network. Another feature of the present invention is an interface architecture capable of supporting external address filters which in turn are capable of supporting spanning tree and source routing algorithms. Still another feature of the present invention is a CRC checker having improved testability such that burdensome computations for input bit test patterns are no longer required. Still another feature of the present invention is a first-in, first-out memory register having validity bits associated with each stored data byte, such that data bytes may be indiscriminately stored, regardless of their validity, and invalid data bytes are discarded during retrieval of the stored data bytes.

Network Interconnect Device And Protocol For Communicating Data Among Packet Forwarding Devices

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US Patent:
60234717, Feb 8, 2000
Filed:
Feb 27, 1998
Appl. No.:
9/032306
Inventors:
Stephen R. Haddock - Los Gatos CA
Herb Schneider - San Jose CA
Curt Berg - Los Altos CA
Daniel J. Cimino - Oak Park CA
Siddharth Khattar - Goleta CA
Matthew T. Knudstrup - Oak Park CA
Mark Thomas Lytwyn - Redondo Beach CA
Aaron C. Tyler - Thousand Oaks CA
Michael Yip - Sunnyvale CA
Assignee:
Extreme Networks - Santa Clara CA
International Classification:
H04L 1256
US Classification:
370426
Abstract:
A network interconnect device and message exchange protocol for forwarding data among packet forwarding devices are provided. According to one aspect of the present invention, data is forwarded between a first and second packet forwarding device coupled to an interconnect device. The interconnect device receives a menu message from the first packet forwarding device that indicates one or more types of data that are awaiting transmission on the first packet forwarding device. Based upon the menu message, the interconnect device transmits an order message selecting a type of data of the one or more types of data awaiting transmission to the first packet forwarding device. The interconnect device receives a message from the first packet forwarding device containing data of the type selected by the order message. The interconnect device then forwards the data to the second packet forwarding device. According to another aspect of the present invention, data is forwarded among multiple packet forwarding devices through an interconnect device by selecting a configuration of the interconnect device based upon ports to which the packet forwarding devices have data to transfer.

Repeater Interface Controller With A Partitioning Port State Machine

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US Patent:
52933750, Mar 8, 1994
Filed:
Aug 14, 1992
Appl. No.:
7/930751
Inventors:
Charles A. Moorwood - Sunnyvale CA
Charan J. Singh - Fairfield CA
Dennis E. Holland - Morgan Hill CA
Daniel J. Cimino - Mountain View CA
Howard Q. Vo - San Jose CA
Vickie M. Yeung - San Francisco CA
David Crosbie - Erskine, GB6
Haresh K. Shah - Pleasanton CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H04J 326
US Classification:
370 131
Abstract:
A repeater interface controller receives a data packet at one of a plurality of port nodes from an associated segment of a local area network. The port nodes determine a priority port node, if more than one port node receives a data packet at substantially the same time, and transmit the data packet from the priority port node to a central node. The central node receives the data packet, repeats the data packet from the priority node, and transmits the repeated data packet to the non-priority port nodes. Each non-priority port node receives the repeated data packet and transmits the repeated data onto its associated segment. Each port node further includes a partitioning port state machine which monitors its associated segment and partitions the segment from the repeater interface controller when the partitioning port state machine detects a collision in a predetermined number of consecutive data packets. The partitioning port state machine detects collisions in each packet from a beginning of the data packet until an end of the data packet.
Daniel J Cimino from Las Vegas, NV, age ~71 Get Report