Search

Dana D Street

from San Francisco, CA
Age ~55
Get Report
Also known as:
Dana Dean Street, Dana S Carpenter, Dan A Carpenter
Related to:
Kelly S Turner, 61Kennie StreetNevaeh Street, 33Shawn A Street, 63Kevin Streets, 65Veda Street, 76Sophia StreetDante Street, 43Arvel StreetArvel D Street, 59Sable Street Kharisma, 33Ryan Street, 34
Connected to:
Aimee Street, 33Amy W Street, 47Annette A Street, 87Arielle J Street, 34Bobby G Street, 50Brandi T Street, 39Brandie L Street, 54Briana L Street, 53Cara L Street, 38Cher R Street, 59

Dana Street Phones & Addresses

  • San Francisco, CA
  • Chatsworth, CA
  • Pasadena, CA
  • 7056 Calvin Ave, Reseda, CA 91335 (818) 708-0860
  • Los Angeles, CA
  • Oakland, CA
  • San Pablo, CA
  • San Gabriel, CA

Work

Company: Martha's vineyard museum May 2009 Address: Edgartown, MA Position: Library assistant

Resumes

Resumes

Dana Street Photo 1

Library Assistant At Martha's Vineyard Museum

View page
Position:
Library Assistant at Martha's Vineyard Museum
Location:
United States
Work:
Martha's Vineyard Museum - Edgartown, MA since May 2009
Library Assistant

Publications

Us Patents

High Speed Memory Cell

View page
US Patent:
39900568, Nov 2, 1976
Filed:
Oct 2, 1975
Appl. No.:
5/618982
Inventors:
James A. Luisi - Anaheim CA
Clarence W. Padgett - Fountain Valley CA
Dana C. Street - Placentia CA
Assignee:
Rockwell International Corporation - El Segundo CA
International Classification:
G11C 1140
US Classification:
340173R
Abstract:
An improved very high speed, static random access memory cell disclosed which is comprised of complementary metal oxide semiconductor field effect transistors which may be formed by silicon on sapphire techniques. To maximize the speed of the read operation while, at the same time, decreasing the overall cell area and consequently the cost, the cell is made highly non-symmetrical in design. As an example, selected ones of the semiconductor transistors may have reduced channel widths with respect to one another.

High Speed-Low Cost, Clock Controlled Cmos Logic Implementation

View page
US Patent:
39821382, Sep 21, 1976
Filed:
Oct 9, 1974
Appl. No.:
5/513368
Inventors:
James A. Luisi - Anaheim CA
Clarence W. Padgett - Fountain Valley CA
Dana C. Street - Placentia CA
Assignee:
Rockwell International Corporation - El Segundo CA
International Classification:
H03K 1908
H03K 1936
US Classification:
307205
Abstract:
A uniquely arranged, clock-controlled integrated circuit is disclosed as a building block for implementing Boolean logic functions. The circuit has a minimum number of components and a design to yield a low cost, high speed operation. The circuit may also include an efficient signal inversion and amplification stage, where such is required.

Memory Output Circuit

View page
US Patent:
39927032, Nov 16, 1976
Filed:
Aug 13, 1975
Appl. No.:
5/604517
Inventors:
James A. Luisi - Anaheim CA
Clarence W. Padgett - Fountain Valley CA
Dana C. Street - Placentia CA
Assignee:
Rockwell International Corporation - El Segundo CA
International Classification:
G11C 1140
US Classification:
340173R
Abstract:
A unique memory output integrated circuit disclosed including a memory output driver having an output terminal at which data may be read, a gated power amplifier, and a single ended multiplexer stage which, in the preferred embodiment, is adapted to be interfaced with a random access memory array comprised of a plurality of discrete, non-symmetrical memory cells. The integrated circuit is designed so that the space consumed thereby and the corresponding cost of production can be minimized.

Cmos Boolean Logic Mechanization

View page
US Patent:
39860426, Oct 12, 1976
Filed:
Dec 23, 1974
Appl. No.:
5/535643
Inventors:
Clarence W. Padgett - Westminster CA
James A. Luisi - Anaheim CA
Dana C. Street - Placentia CA
Assignee:
Rockwell International Corporation - El Segundo CA
International Classification:
H03K 1908
H03K 1912
H03K 1928
H03K 1938
US Classification:
307205
Abstract:
Unique, relatively simplified circuits employing complementary metal oxide semiconductor transistors and suitable diode means to mechanize the Boolean functions A. sup. B and A+B and combinations thereof. In a preferred embodiment, the transistors and diodes may be fabricated by silicon-on-sapphire integrated circuit techniques. The circuits obviate the need for a conventional NOR or NAND gate which is common to logic gating arrangements of the prior art. Hence, the number of components and the corresponding cost of the circuit are reduced while the operating speed thereof is increased.

Cmos Boolean Logic Circuit

View page
US Patent:
41852095, Jan 22, 1980
Filed:
Feb 2, 1978
Appl. No.:
5/874601
Inventors:
Dana C. Street - Placentia CA
Assignee:
Rockwell International Corporation - El Segundo CA
International Classification:
H03K 1908
H03K 1912
H03K 1922
H03K 1930
US Classification:
307218
Abstract:
Compact and high speed logic circuits that utilize CMOS technology to perform the Boolean operations A. multidot. B and A+B. The presently disclosed logic circuits are comprised of a field effect transistor and first and second logic performing diodes which are uniquely interconnected with one another so as to reduce the number of circuit components and to increase the operating speed relative to conventional logic circuits.

Mos Inverting Power Driver Circuit

View page
US Patent:
40428389, Aug 16, 1977
Filed:
Jul 28, 1976
Appl. No.:
5/709464
Inventors:
Dana C. Street - Placentia CA
Clarence W. Padgett - Westminster CA
Assignee:
Rockwell International Corporation - El Segundo CA
International Classification:
H03K 1760
US Classification:
307270
Abstract:
An improved, compact high-speed inverting power driver fabricated from field effect transistors and capable of driving a relatively heavy load to full -V. sub. DD power supply voltage. The power driver includes a pair of positive feedback circuits having respective bootstrap capacitors arranged therein. The bootstrap capacitors are initially precharged, and the feedback paths act to substantially boost the voltage applied to operate a driver transistor so as to enable the load to be ultimately driven to a full -V. sub. DD voltage level via the conduction path of the driver transistor.
Control profile
Dana D Street from San Francisco, CA, age ~55 Get Report