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Damian A Carver

from Santa Clara, CA
Age ~65
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Also known as:
Damian D Carver, Damiaw A Carver
Related to:
Jr ZeledonBarbara BednarJimmy ZeledonAmanda Zeledon, 35Philip Bednar
Connected to:
Aleshia A Carver, 35Amber N Carver, 39Angelo Carver, 34Bailey M Carver, 31Barb S Carver, 57Belinda J Carver, 55Bethany J Carver, 56Britnee N Carver, 37Brook B Carver, 36Bruce E Carver, 72

Damian Carver Phones & Addresses

  • Santa Clara, CA
  • Colorado Springs, CO
  • 4815 Lake Waterford Way W, Melbourne, FL 32901
  • Palm Bay, FL
  • Irving, TX
  • Boise, ID
  • 426 W Cheyenne Rd, Colorado Springs, CO 80906 (719) 271-2474

Work

Company: Micrel Dec 2007 to Feb 2013 Position: Director of hbw technology development

Education

Degree: Bachelors, Bachelor of Science School / High School: Purdue University 1978 to 1984

Skills

Failure Analysis • Analog • Ic • Asic • Semiconductors • Mixed Signal • Electronics • Analog Circuit Design • Cmos • Debugging • Simulations • Soc • Bicmos • Microelectronics • Circuit Design • Semiconductor Industry • Vlsi • Rf • Microcontrollers • Integrated Circuits

Languages

English

Interests

Animal Welfare • Environment • Science and Technology

Emails

r***[email protected]

Industries

Semiconductors

Resumes

Resumes

Damian Carver Photo 1

Damian Carver

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Location:
426 west Cheyenne Rd, Colorado Springs, CO 80906
Industry:
Semiconductors
Work:
Micrel Dec 2007 - Feb 2013
Director of Hbw Technology Development
Atmel Corporation Jan 1998 - Dec 2006
Bicmos Technology Development Director
Sgs-Thomson Microelectronics May 1994 - Dec 1997
Device Engineering Section Manager
National Semiconductor 1984 - 1994
Staff Engineer
Education:
Purdue University 1978 - 1984
Bachelors, Bachelor of Science
Skills:
Failure Analysis
Analog
Ic
Asic
Semiconductors
Mixed Signal
Electronics
Analog Circuit Design
Cmos
Debugging
Simulations
Soc
Bicmos
Microelectronics
Circuit Design
Semiconductor Industry
Vlsi
Rf
Microcontrollers
Integrated Circuits
Interests:
Animal Welfare
Environment
Science and Technology
Languages:
English

Publications

Us Patents

Low-Voltage Single-Layer Polysilicon Eeprom Memory Cell

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US Patent:
7144775, Dec 5, 2006
Filed:
May 18, 2004
Appl. No.:
10/848763
Inventors:
Muhammad I. Chaudhry - Colorado Springs CO, US
Damian A. Carver - Colorado Springs CO, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
H01L 21/336
US Classification:
438258, 438157, 438223, 438238, 438257, 438323, 257314, 257315, 257316, 257318
Abstract:
The present invention is an electronic memory cell and a method for the cell's fabrication comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be programmable with a voltage about equal to a voltage on the bit line.

Low-Cost, Low-Voltage Single-Layer Polycrystalline Eeprom Memory Cell Integration Into Bicmos Technology

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US Patent:
7208795, Apr 24, 2007
Filed:
May 24, 2005
Appl. No.:
11/136140
Inventors:
Damian A. Carver - Colorado Springs CO, US
Muhammad I. Chaudhry - Colorado Springs CO, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
H01L 29/788
H01L 21/8238
US Classification:
257315, 257314, 257E2917, 257E29309, 438201, 438288, 438573
Abstract:
An EEPROM memory transistor having a floating gate. The floating gate is formed using a BiCMOS process and has a first sinker dopant region proximate to a tunnel diode window, and a second sinker dopant region proximate to a coupling capacitor region. An optional third sinker region may be formed proximate to a source junction of the EEPROM memory transistor. Also, a shallow trench isolation (STI) region may be formed between the first and second sinker dopant regions.

Bandgap Engineered Mono-Crystalline Silicon Cap Layers For Sige Hbt Performance Enhancement

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US Patent:
7300849, Nov 27, 2007
Filed:
Nov 4, 2005
Appl. No.:
11/266797
Inventors:
Darwin Gene Enicks - Colorado Springs CO, US
Damian Carver - Colorado Springs CO, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
H01L 21/331
US Classification:
438316, 438312
Abstract:
A method for fabricating a heterojunction bipolar transistor (HBT) is provided. The method includes providing a substrate including a collector region; forming a compound base region over the collector region; forming a cap layer overlying the compound base region including doping the cap layer with a pre-determined percentage of at least one element associated with the compound base region; and forming an emitter region over the cap layer.

Low-Voltage Single-Layer Polysilicon Eeprom Memory Cell

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US Patent:
7408812, Aug 5, 2008
Filed:
Oct 11, 2006
Appl. No.:
11/548444
Inventors:
Muhammad I. Chaudhry - Colorado Springs CO, US
Damian A. Carver - Colorado Springs CO, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G11C 11/34
US Classification:
36518528, 36518524
Abstract:
The present invention is an electronic memory cell and a method for the cell's fabrication comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be programmable with a voltage about equal to a voltage on the bit line.

Bandgap And Recombination Engineered Emitter Layers For Sige Hbt Performance Optimization

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US Patent:
7651919, Jan 26, 2010
Filed:
Nov 4, 2005
Appl. No.:
11/267553
Inventors:
Darwin Gene Enicks - Colorado Springs CO, US
Damian Carver - Colorado Springs CO, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
H01L 21/331
H01L 21/8222
US Classification:
438312, 438320, 438350, 257197, 257E21371
Abstract:
A method for fabricating a heterojunction bipolar transistor (HBT) is provided. The method includes providing a substrate including a collector region; forming a compound base region over the collector region; and forming an emitter region over the compound base region including forming a first emitter layer within the emitter region and doping the first emitter layer with a pre-determined percentage of at least one element associated with the compound base region. In one implementation, an emitter region is formed including multiple emitter layers to enhance a surface recombination surface area within the emitter region.

Integrated Circuit Structures Containing A Strain-Compensated Compound Semiconductor Layer And Methods And Systems Related Thereto

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US Patent:
8530934, Sep 10, 2013
Filed:
Oct 11, 2010
Appl. No.:
12/901867
Inventors:
Darwin G. Enicks - Painted Post NY, US
John Taylor Chaffee - Colorado Springs CO, US
Damian A. Carver - Santa Clara CA, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
H01L 21/02
US Classification:
257190, 438312, 438309, 257235, 257E29068, 257E21371
Abstract:
A method for pseudomorphic growth and integration of an in-situ doped, strain-compensated metastable compound base into an electronic device, such as, for example, a SiGe NPN HBT, by substitutional placement of strain-compensating atomic species. The invention also applies to strained layers in other electronic devices such as strained SiGe, Si in MOS applications, vertical thin film transistors (VTFT), and a variety of other electronic device types. Devices formed from compound semiconductors other than SiGe, such as, for example, GaAs, InP, and AlGaAs are also amenable to beneficial processes described herein.

Method For Growth And Optimization Of Heterojunction Bipolar Transistor Film Stacks By Remote Injection

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US Patent:
20060292809, Dec 28, 2006
Filed:
Jun 23, 2005
Appl. No.:
11/166287
Inventors:
Darwin Enicks - Colorado Springs CO, US
Damian Carver - Colorado Springs CO, US
International Classification:
H01L 21/331
US Classification:
438350000, 438341000, 438312000
Abstract:
A method, and a resulting device, for fabricating a heterojunction bipolar transistor (HBT). HBT devices have a high transconductance typical of bipolar devices and are additionally capable of high-power operation. To achieve the aforementioned characteristics, HBT devices are generally of the npn type, preferably with a thin, heavily doped base. The thin, heavily doped base maintains a low base-spreading resistance, leading to a high maximum oscillation frequency. In order to maintain a high doping concentration while minimizing outdiffusion of the dopant material, carbon is remotely doped into the base region. Details of the carbon dopant techniques and procedures are described with respect to fabrication of an exemplary HBT device.

Low-Voltage Single-Layer Polysilicon Eeprom Memory Cell

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US Patent:
20070087550, Apr 19, 2007
Filed:
Oct 11, 2006
Appl. No.:
11/548512
Inventors:
Muhammad Chaudhry - Colorado Springs CO, US
Damian Carver - Colorado Springs CO, US
Assignee:
ATMEL CORPORATION - San Jose CA
International Classification:
H01L 21/44
H01L 21/4763
US Classification:
438617000, 438618000
Abstract:
The present invention is an electronic memory cell and a method for the cell's fabrication comprising a The first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be programmable with a voltage about equal to a voltage on the bit line.
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Damian A Carver from Santa Clara, CA, age ~65 Get Report