Dale R Beucler

6882562, Apr 19, 2005

Aug 7, 2002

10/213510

Dale Beucler - Fort Collins CO, US

Agilent Technologies, Inc. - Palo Alto CA

G11C011/00

365154, 365233, 36523005

A method and apparatus operable to provide pseudo 2-port RAM functionality using 1-port memory cells. A pseudo 2-port RAM functionality is provided using an array of 1-port memory cells to perform read and write operations during a single clock cycle. Control logic is used to determine when the read and write operations occur. The pseudo 2-port RAM uses the control logic to divide the clock cycle into four phases in accordance with a preferred embodiment. The first phase is used to set up the addresses and register values, the second phase is used to prepare for the read operation, the third phase is used to perform the read operation and prepare for the write operation, and the fourth phase performs the write operation.

6914833, Jul 5, 2005

Oct 6, 2003

10/679928

Louise A. Koss - Ft. Collins CO, US
Mary Louis Nash - Fort Collins CO, US
Dale Beucler - Ft Collins CO, US

Agilent Technologies, Inc. - Palo Alto CA

G11C007/00
G11C029/00
G11C008/00

365200, 365201, 36518902, 36518905, 36518912, 36523002, 36523003, 36523008

An apparatus for the on-chip, soft repair of random access memory arrays. In representative embodiments, circuitry is disclosed which provides the ability to soft repair defective random access memory arrays. The disclosed techniques for repair of random access memory arrays do not use techniques such as laser repair in the removal of defective parts of the integrated circuit and its replacement with a redundant part. No additional processing steps are involved. The circuitry necessary to repair defects in random access memory arrays is included on-chip in the input/output blocks of the RAM.

7055075, May 30, 2006

Dec 5, 2001

10/008382

Louise A. Koss - Ft. Colllins CO, US
Mary Louise Nash - Fort Collins CO, US
Dale Beucler - Ft Collins CO, US

Avago Techologies General IP Pte. Ltd. - Singapore

G11C 29/00

714718

An apparatus for the on-chip testing of random access memory arrays. In representative embodiments, embedded circuitry provides the ability to test random access memory arrays on-chip without requiring substantial area on the chip. The circuits are inherently located closer to the tested area which reduces propagation delay errors. These advantages have been obtained by locating the circuitry necessary to perform such test in the addressing and input/output blocks of the RAM.

7519875, Apr 14, 2009

Aug 22, 2005

11/208681

Jeffrey R. Rearick - Fort Collins CO, US
Louise A. Koss - Fort Collins CO, US
Mary Louise Nash - Fort Collins CO, US
Dale R. Beucler - Fort Collins CO, US

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

G06F 3/00
G06F 11/00

714710, 714 8

The invention provides a method and an apparatus for enabling a user to determine whether a defective location in a memory device of an integrated circuit (IC) has been remapped to a location in a redundant memory portion of the memory device. Users are provided with the ability to observe the remapping, and preferably, to determine which locations in the memory device have been remapped. The memory device includes remapping observation logic that causes bits associated with remapping to be output from the memory device. Preferably, a computer receives the remapping bits and displays a description of any remapping on a display monitor. Therefore, not only is a user able to determine whether remapping has occurred, but also which locations in the memory device have been remapped.

8281190, Oct 2, 2012

Aug 2, 2009

12/534150

Rosalee Gunderson - Fort Collins CO, US
Dale Beucler - Fort Collins CO, US
Louise A. Koss - Fort Collins CO, US

Avago Technologies Enterprise IP (Singapore) Pte. Ltd. - Singapore

G11C 29/00
G06F 11/00
G01R 31/28

714710, 714 30, 714 42, 714718, 714711, 714726, 714727, 714729, 714736, 714742

An interface processes memory redundancy data on an application specific integrated circuit (ASIC) with self-repairing random access memory (RAM) devices. The interface includes a state machine, a counter, and an array of registers. The state machine is coupled to a redundancy chain. The redundancy chain includes coupled redundant elements of respective memory elements on the ASIC. In a shift-in mode, the interface shifts data from each of the elements in the redundancy chain and compresses the data in the array of registers. The interface communicates with a test access port coupled to one or more eFuse devices to store and retrieve the compressed data. In a shift-out mode, the interface decompresses the data stored in the array of registers and shifts the decompressed data to each unit in the redundancy chain. The interface functions absent knowledge of the number, bit size and type of self-repairing RAM devices in the redundancy chain.

20030107925, Jun 12, 2003

Dec 12, 2001

10/021614

Louise Koss - Ft. Collins CO, US
Mary Nash - Fort Collins CO, US
Dale Beucler - Ft Collins CO, US

G11C007/00

365/200000

An apparatus for the on-chip, soft repair of random access memory arrays. In repesentative embodiments, circuitry is disclosed which provides the ability to soft repair defective random access memory arrays. The disclosed techniques for repair of random access memory arrays do not use techniques such as laser repair in the removal of defective parts of the integrated circuit and its replacement with a redundant part. No additional processing steps are involved. The circuitry necessary to repair defects in random access memory arrays is included on-chip in the input/output blocks of the RAM.

20080183984, Jul 31, 2008

Jan 31, 2007

11/700335

Dale Beucler - Fort Collins CO, US
Allen Brown - Corvallis OR, US

G06F 12/00

711155

An integrated circuit includes an array of memory cells, addressing circuitry, and timing and control logic. The array of memory cells is configured to store data bits. The addressing circuitry is configured to address multiple locations of memory cells in response to a clock signal. The timing and control logic is responsive to the clock signal and configured to control a read-modify-write operation to read a first group of data bits from a first address location, modify at least one of the bits of the first group, and write the modified first group to the first address location. The read-modify-write operation is performed within one cycle of the clock signal.

6539507, Mar 25, 2003

Nov 10, 1999

09/437813

Christopher M Juenemann - Aurora CO
Bradley J Goertzen - Ft. Collins CO
Rory L Fisher - Fort Collins CO
Randy L Fiscus - Ft. Collins CO
Brian C Miller - Fort Collins CO
Peter J Meier - Fort Collins CO
Joel Buck-Gengler - Longmont CO
Kenneth S Bower - Ft. Collins CO
Michael R Diehl - Fort Collins CO
Dale R Beucler - Fort Collins CO

Agilent Technologies, Inc. - Palo Alto CA

G01R 3128

714726

An integrated circuit incorporating test access provisions and a system addressable command control register; and provisions for selectably enabling and accessing one or the other for purposes of evaluating integrated circuit functionality.