Da A Zhang

7018901, Mar 28, 2006

Sep 29, 2004

10/954121

Mariam G. Sadaka - Austin TX, US
Ted R. White - Austin TX, US
Alexander L. Barr - Crolles, FR
Venkat R. Kolagunta - Austin TX, US
Victor H. Vartanian - Dripping Springs TX, US
Da Zhang - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/336

438285, 438300, 438290

A semiconductor device () is formed by positioning a gate () overlying a semiconductor layer () of preferably silicon. A semiconductor material () of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel () in which a stressor material layer () is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

7067868, Jun 27, 2006

Sep 29, 2004

10/952676

Mariam G. Sadaka - Austin TX, US
Ted R. White - Austin TX, US
Alexander L. Barr - Crolles, FR
Venkat R. Kolagunta - Austin TX, US
Victor H. Vartanian - Dripping Springs TX, US
Da Zhang - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 27/108

257296, 257327

A semiconductor device () is formed by positioning a gate () overlying a semiconductor layer () of preferably silicon. A semiconductor material () of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel () in which a stressor material layer () is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

7226820, Jun 5, 2007

Apr 7, 2005

11/101354

Da Zhang - Austin TX, US
Jing Liu - Austin TX, US
Ted R. White - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/00

438149, 438150, 438162, 438163, 438164, 257E2926

A semiconductor fabrication process includes forming a gate electrode () overlying a gate dielectric () overlying a semiconductor substrate (). First spacers () are formed on sidewalls of the gate electrode (). First s/d trenches () are formed in the substrate () using the gate electrode () and first spacers () as a mask. The first s/d trenches () are filled with a first s/d structure (). Second spacers () are formed on the gate electrode () sidewalls adjacent the first spacers (). Second s/d trenches () are formed in the substrate () using the gate electrode () and the second spacers () as a mask. The second s/d trenches () are filled with a second s/d structure (). Filling the first and second s/d trenches () preferably includes growing the s/d structures using an epitaxial process. The s/d structures () may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.

7238561, Jul 3, 2007

Aug 2, 2005

11/195510

Da Zhang - Austin TX, US
Veer Dhandapani - Round Rock TX, US
Brian Goolsby - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/336

438197, 438296, 438481, 438E21431

A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises a substrate () with a gate structure () disposed thereon, wherein the gate structure comprises a gate electrode () and at least one spacer structure (), and wherein the substrate comprises a first semiconductor material. A first trench () is created in the substrate adjacent to the gate structure through the use of a first etch. The gate electrode is then etched with a second etch. Preferably, the minimum cumulative reduction in thickness of the gate electrode from the first and second etches is d, the maximum depth of the first and second trenches after the first and second etches is d, and d≧d.

7282415, Oct 16, 2007

Mar 29, 2005

11/092291

Da Zhang - Austin TX, US
Yasuhito Shiho - Austin TX, US
Veer Dhandapani - Round Rock TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/336

438300, 257E21345, 257E21336, 257E21427, 257E21193

A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the control electrode are implanted to form first and second doped current electrode regions, a portion of each of the first and second doped current electrode regions being driven to underlie both the insulating layer and the control electrode in a channel region of the semiconductor device. The first and second doped current electrode regions are removed from the semiconductor substrate except for underneath the control electrode and the insulating layer to respectively form first and second trenches. An insitu doped material containing a different lattice constant relative to the semiconductor substrate is formed within the first and second trenches to function as first and second current electrodes of the semiconductor device.

7413970, Aug 19, 2008

Mar 15, 2006

11/375894

Da Zhang - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 29/06
H01L 21/3205

438595, 257E21014, 257 18, 257213

An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.

7446026, Nov 4, 2008

Feb 8, 2006

11/349595

Da Zhang - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/3205
H01L 21/4763
H01L 21/8238
H01L 21/8234

438592, 438199, 438275, 257E21198

A method for forming a semiconductor device includes providing a semiconductor substrate having a first doped region and a second doped region, providing a dielectric over the first doped region and the second doped region, and forming a first gate stack over the dielectric over at least a portion of the first doped region. The first gate stack includes a metal portion over the dielectric, a first in situ doped semiconductor portion over the metal portion, and a first blocking cap over the in situ doped semiconductor portion. The method further includes performing implantations to form source/drain regions adjacent the first and second gate stack, where the first blocking cap has a thickness sufficient to substantially block implant dopants from entering the first in situ doped semiconductor portion. Source/drain embedded stressors are also formed.

7479422, Jan 20, 2009

Mar 10, 2006

11/373536

Brian A. Winstead - Austin TX, US
Ted R. White - Austin TX, US
Da Zhang - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/336

438197, 438222, 438299, 257E21431, 257E21633, 257E21634

A method for forming a semiconductor device includes providing a substrate region having a first material and a second material overlying the first material, wherein the first material has a different lattice constant from a lattice constant of the second material. The method further includes etching a first opening on a first side of a gate and etching a second opening on a second side of the gate. The method further includes creating a first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the first in-situ doped epitaxial region is created using the second material. The method further includes creating a second in-situ n-type doped expitaxial region overlying the first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the second in-situ n-type doped epitaxial region is created using the second material.