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Craig R Fossey

from Phoenix, AZ
Age ~66
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Also known as:
Craig Robert Fossey, Cgaig R Fossey, Robert C Fossey
Related to:
Jennifer Diane Stambaugh, 53Jessie Ignjatovic, 57Barbara M FosseyFam FosseyBeatriz E Garcia, 66Sandra T Garcia, 61Jessie Ignjatovic, 56Robert C Fossey, 96Angela M Meland, 44Famtr FosseyJesse A Ignjatovic, 56Noren B Meland, 71Juan M GarciaSue Meland, 81
Connected to:
Colin D Fossey, 35Dustin D Fossey, 42Robert J Fossez, 84Terence A Fossgreen, 61Judith W Fosshage, 84Gregory H Fossheim, 69Anthony W Fossi, 35Carolina Fossi, 52Lisa A Fossi, 55Monica S Fossi, 53

Craig Fossey Phones & Addresses

  • Phoenix, AZ
  • Durango, CO
  • 8312 Via De Los Libros, Scottsdale, AZ 85258 (480) 315-1601 (480) 998-4551 (480) 998-7654
  • 8401 80Th St, Scottsdale, AZ 85258 (480) 998-4551
  • 8166 Del Rubi Dr, Scottsdale, AZ 85258 (480) 998-7654

Resumes

Resumes

Craig Fossey Photo 1

Information Assurance System Engineer

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Location:
3200 north 39Th St, Phoenix, AZ 85018
Industry:
Telecommunications
Work:
General Dynamics Mission Systems
Information Assurance System Engineer
Motorola 1982 - 2008
Electronics Engineer
Education:
University of Arizona 1978 - 1981
Bachelors, Bachelor of Science In Electrical Engineering, Electronics Engineering, Electronics University of Minnesota 1976 - 1978
Skills:
Systems Engineering
Cissp
Information Assurance
Requirements Analysis
System Architecture
Software Engineering
Embedded Systems
Integration
Clearcase
Embedded Software
Requirements Management
Testing
Engineering Management
Dod
Languages:
English
Spanish
Craig Fossey Photo 2

Craig Fossey

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Craig Fossey Photo 3

Craig Fossey

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Publications

Us Patents

Parallel Cyclic Redundancy Check Circuit

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US Patent:
51034514, Apr 7, 1992
Filed:
Jan 29, 1990
Appl. No.:
7/471318
Inventors:
Craig R. Fossey - Scottsdale AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 1110
US Classification:
371 376
Abstract:
A method and circuitry for generating N-bit parallel CRC code from an N-bit parallel data input source. A generating polynomial function is used to express an array of exclusive-OR gates to which the N-bit parallel data inputs are applied. A plurality of N latches is provided and connected to the exclusive-OR gate array in a feedback fashion to provide the plurality of N-bit parallel CRC codes according to the polynomial function.

Secure Computer With Bus Monitoring System And Methods

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US Patent:
61417572, Oct 31, 2000
Filed:
Jun 22, 1998
Appl. No.:
9/100956
Inventors:
Frank Edward Seeker - Glendale AZ
Craig Robert Fossey - Scottsdale AZ
Assignee:
Motorola, Inc.
International Classification:
G06F 1100
US Classification:
713200
Abstract:
A secure computer system (100) includes a host processor (105) for communicating a datum to a trusted bus (101). A bridge (125) connects the trusted bus (101) to an untrusted bus (102). The bridge (125) conveys the datum from the trusted bus (101) to the untrusted bus (102). A bus access monitor (200) is coupled to the trusted bus (101) and the untrusted bus (102). The bus access monitor (200) performs a method (1000, FIG. 10) for securely monitoring the untrusted bus (102), and asserting an alarm signal when address information associated with the datum fails to compare with predetermined address information. Additionally, the host processor (105) performs a method (300, FIG. 3) for self-testing the bus access monitor.

Encryption Method And System For Portable Data

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US Patent:
56235461, Apr 22, 1997
Filed:
Jun 23, 1995
Appl. No.:
8/494129
Inventors:
Douglas A. Hardy - Mesa AZ
Craig R. Fossey - Scottsdale AZ
Craig R. Balogh - Mesa AZ
Steven R. Tugenberg - Scottsdale AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H04L 932
G06F 306
US Classification:
380 4
Abstract:
A system and method allows portable, encrypted data to be accessible through multiple hosts, including new hosts (14), without requiring a secure link to the new hosts. A split key encryption system encrypts (52) data and stores the encrypted data on a portable device (10). A split of the encryption key is stored (54) in the portable device (10), and another split of the key is stored (54) in a home host (12). A password-modified key is then made (58) by combining a password with the encryption key. This password-modified key is then reduced (58), with one split being stored on the host (12) and another split stored on the portable device (10). Data can be accessed with a new host (14) by transferring (78) the host password-modified split to the new host (14) and entering (80) the password into the portable device (10).

Secure Terminal And Method Of Communicating Messages Among Processing Systems Internal Thereto

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US Patent:
61122297, Aug 29, 2000
Filed:
May 1, 1998
Appl. No.:
9/071184
Inventors:
Douglas Allan Hardy - Scottsdale AZ
Craig Robert Fossey - Scottsdale AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 1300
US Classification:
709206
Abstract:
A secure terminal includes a host (105) and slaves (125) which send and receive messages via a peripheral component interconnect (PCI) bus (130). The host allows slaves to receive messages from the host and send messages to the host. The host prevents slave-to-slave communication of messages. The host and each slave include interface logic (120) coupled to the PCI bus and a memory (200) for coupling a processor (110) to the interface logic (120). Each dual-port RAM (200) includes a first memory portion for receiving messages from a sender and a second memory portion for storing messages to be transmitted to a receiver.
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Craig R Fossey from Phoenix, AZ, age ~66 Get Report