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Craig Jay Corsetto

from Oakland, MD
Age ~71
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Also known as:
Craig J Corsetto, Criag J Corsetto, Craig J Corsette
Phone and address:
677 Paradise Ridge Rd, Mountain Lake Park, MD 21550
(301) 387-2159
Related to:
Sharyl P Corsetto, 68Danielle E Corsetto, 43Edward B Parker, 97Jeffrey K Parker, 70Brent J Corsetto, 41Roberta L Parker, 95
Connected to:
Amy L Corsetti, 61Annette M Corsetti, 58Anthony J Corsetti, 38Brian D Corsette, 57Briana A Corsetti, 36David L Corsetti, 68Debra L Corsetti, 74Domenic Corsetti, 80Giancarlo Corsetti, 64Joseph F Corsetto, 70

Craig Corsetto Phones & Addresses

  • 677 Paradise Ridge Rd, Oakland, MD 21550 (301) 387-2159
  • San Jose, CA
  • Gaithersburg, MD
  • 3141 Pheasant Run, Ijamsville, MD 21754 (301) 865-5670
  • Germantown, MD

Work

Company: Boeing company - Germantown, MD Feb 2003 Position: Senior system engineer

Education

School / High School: Montgomery College- Germantown, MD 1989 Specialities: Towards BSEE in General Education

Skills

RF system design
RF/Microwave circui... • Project Engineer leading small teams on ...

Emails

c***[email protected]

Resumes

Resumes

Craig Corsetto Photo 1

Craig Corsetto Ijamsville, MD

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Work:
Boeing Company
Germantown, MD
Feb 2003 to Feb 2014
Senior System Engineer
Watkins Johnson Company
Gaithersburg, MD
Jul 1984 to Feb 2003
member technical staff
Education:
Montgomery College
Germantown, MD
1989 to 1990
Towards BSEE in General Education
Foot Hill College
Los Altos, CA
1979 to 1981
Towards BSEE in Mathematics
Old Dominion University
Norfolk, VA
1977 to 1977
Towards BSEE in General Education
Cabrillo College
Aptos, CA
1971 to 1972
Towards BSEE in Electronics
Skills:
RF system design<br/>RF/Microwave circuit design and PCB layout<br/>RF Lead, Project Engineer leading small teams on product development<br/>System design of miniature SDR products

Publications

Us Patents

Phase Locked Loop For Clock Extraction In Gigabit Rate Data Communication Links

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US Patent:
49264478, May 15, 1990
Filed:
Nov 18, 1988
Appl. No.:
7/273302
Inventors:
Craig Corsetto - Ijamsville MD
Tom Hornak - Portola Valley CA
Rasmus Nordby - Horsholm, DE
Rick C. Walker - Palo Alto CA
Chu Yen - Palo Alto CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
H04L 733
US Classification:
375120
Abstract:
A family of Phase Locked Loop circuits and methods for extraction of a clock signal from a digital data stream, for example as received by a data communication link receiver is taught. The circuits of this invention are particularly advantageous in gigabit rate links where the propagation delay of digital circuits is comparable to the duration of a bit time interval and therefore careful matching of clock extracting and data sampling circuit topology is required. In certain embodiments, a frequency detector is included making the structure suitable for use in situations where there is a large fractional difference between the incoming data rate and the free running frequency of the receiver VCO. Such is the case when both the incoming data rate and the receiver VCO frequency are not controlled by a precision element such as a crystal or a Surface Acoustic Wave device.

Dc-Free Line Code For Arbitrary Data Transmission

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US Patent:
50220519, Jun 4, 1991
Filed:
Nov 2, 1988
Appl. No.:
7/266459
Inventors:
Douglas Crandall - Berkeley CA
Steven R. Hessel - Campbell CA
Thomas Hornak - Portola Valley CA
Rasmus Nordby - Horsholm, DK
Kent H. Springer - Westford MA
Craig Corsetto - Ijamsville MD
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
H04L 2506
H04L 2532
US Classification:
375 19
Abstract:
Means and structure for encoding binary data ensures that, on average, the encoded data provides a balanced data stream having an equal number of logical one and logical zero bits. An indicator bit of known value is appended to N data bits, forming a group of N+1 bits. The polarity of this group is determined, i. e. whether the group contains more ones than zeros. The cumulative polarity of all bits sent over the communication link is also maintained. When the polarity of the group is the same as the cumulative polarity, all bits in the group are inverted and the inverted group is transmitted. Otherwise the bits in the group are transmitted in their original form. To decode the transmitted bits, the bit stream is framed to separate each series of N+1 bits. The value of the indicator bit on the receiver side of the communication link indicates whether the group has been inverted. If the group has been inverted, it is reinverted on the receiver side of the link to provide the N data bits in their original form.
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Craig Jay Corsetto from Oakland, MD, age ~71 Get Report