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Craig A Bellows

from San Antonio, TX
Age ~76
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Also known as:
Craig A Bellow
Phone and address:
9126 Cap Mountain Dr, San Antonio, TX 78255
(210) 698-2340
Related to:
Susanna D Snowdy, 67Jacob TorresLana Belows, 76Bethany A Bishop, 46Lana A Bellows, 70Jeannette TorresDavid J Bellows, 39Breanna BellowsBreanna L Bellows, 41Daniel B Bishop, 44Betsy N Bellows, 73John G Torres, 46Bethany BishopLana Bellows, 76
Connected to:
Amber R Bellows, 46Anne E Bellows, 51Belinda P Bellows, 66Boyd K Bellows, 71Carl J Bellows, 102Carol H Bellows, 84Charlene M Bellows, 58Christopher N Bellows, 65Cynthia C Bellows, 49Donna J Bellows, 52

Craig Bellows Phones & Addresses

  • 9126 Cap Mountain Dr, San Antonio, TX 78255 (210) 698-2340 (210) 698-2490 (210) 698-5509
  • 7430 Lake Breeze Dr, Fort Myers, FL 33907 (239) 689-5452
  • 7430 Lake Breeze Dr APT 307, Fort Myers, FL 33907 (239) 689-5452
  • 4400 Lazio Way APT 207, Fort Myers, FL 33901
  • Perrysburg, OH
  • San Diego, CA
  • Orlando, FL
  • Lee, FL

Work

Company: Bellowspcrepair May 2010 Address: Fort Myers, Florida Position: Grandmaster gamer

Education

School / High School: Rensselaer Polytechnic Institute

Industries

Computer Games

Resumes

Resumes

Craig Bellows Photo 1

Retired Old Guy

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Position:
Grandmaster Gamer at BellowsPCRepair
Location:
Fort Myers, Florida
Industry:
Computer Games
Work:
BellowsPCRepair - Fort Myers, Florida since May 2010
Grandmaster Gamer
First Solar Apr 2008 - Feb 2010
Manufacturing Engineer
Education:
Rensselaer Polytechnic Institute

Publications

Us Patents

Four Port Tube To Extend The Life Of Quartz Tubes Used For The Well Drive Process

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US Patent:
56054548, Feb 25, 1997
Filed:
Oct 12, 1995
Appl. No.:
8/542090
Inventors:
Craig A. Bellows - San Antonio TX
Curtis M. Herbert - San Antonio TX
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
F27D 1900
US Classification:
432 50
Abstract:
A quartz tube with multiple thermocouple ports arranged along its radius allows for the quartz tube to be rotated while the thermocouple is always placed in the bottom position of the quartz tube. This avoids a problem of the sagging of the quartz tube. When quartz tubes are not rotated, the quartz tubes tend to start sagging from their top. By rotating the quartz tube different portions of the quartz tube are at the top at different times. By using multiple thermocouple ports arranged around the radius of the quartz tube, the thermocouple can be positioned at the bottom of the quartz tube for different orientations of the quartz tube.

Semiconductor Wafer Manufacturing Process With High-Flow-Rate Low-Pressure Purge Cycles

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US Patent:
57286027, Mar 17, 1998
Filed:
Jun 3, 1996
Appl. No.:
8/657148
Inventors:
Craig A. Bellows - San Antonio TX
Landon B. Vines - San Antonio TX
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
H01L 21302
US Classification:
437225
Abstract:
A purge process for an LPCVD TEOS silicon dioxide deposition method uses a series of five purge cycles to allow low-defect wafer processing with less frequent chamber removal and cleaning. The purge process begins by loading dummy wafers into the chamber. Chamber pressure is reduced to below 20 mTorr. A maximal nonreactant gas flow for two minutes is used to dislodge and carry away contaminants such as flakes from silicon dioxide previously deposited on the chamber wall. After the first four of five purge cycles, the method returns to the reduction of chamber pressure, e. g. , by maintaining the vacuum on while the gas sources are turned off. After the fifth cycle, the chamber is slowly filled with nitrogen until ambient pressure is reached. Then the dummy wafers are removed. The system is then ready for processing product wafers with reduced particle counts.

Thermal Trap For Gaseous Materials

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US Patent:
53035585, Apr 19, 1994
Filed:
Jul 30, 1992
Appl. No.:
7/923291
Inventors:
Oscar L. Caton - Boerne TX
Craig A. Bellows - San Antonio TX
Curtis M. Hebert - San Antonio TX
Steve J. Schaper - San Antonio TX
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
B01D 800
US Classification:
62 555
Abstract:
A semiconductor deposition system with thermal trap characterized by a processing chamber, a source of process gas coupled to an inlet of the processing chamber, a thermal trap coupled to an outlet of the processing chamber, and a pump mechanism operative to pump a gas from the process chamber and into the thermal trap. The thermal trap preferably includes an enclosure defining a trap chamber, where an inlet to the trap chamber is coupled to the outlet of the processing chamber, a condensable-solid collection surface located within the trap chamber, a mechanism for maintaining the temperature of the collection surface at or below the temperature at which a gas flowing into the chamber condenses into a solid form, and a mechanism for maintaining the temperature of an inner surface of the enclosure at a temperature above which the gas condenses into a solid form. A method for trapping a gaseous material is characterized by the steps of flowing a gaseous material into a chamber of an enclosure, and maintaining the temperature of a collection surface disposed within the chamber at or below the temperature at which the gaseous material condenses into a solid form. The method preferably also includes the step of maintaining the temperature of an inner surface of the enclosure above the temperature at which the gaseous material condenses into a solid.

Ic Interconnect Formation With Chemical-Mechanical Polishing And Silica Etching With Solution Of Nitric And Hydrofluoric Acids

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US Patent:
60487895, Apr 11, 2000
Filed:
Feb 27, 1997
Appl. No.:
8/807069
Inventors:
Landon B. Vines - San Antonio TX
Craig A. Bellows - San Antonio TX
Walter D. Parmantie - San Antonio TX
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
H01L 21461
US Classification:
438633
Abstract:
An integrated circuit manufacturing method uses chemical-mechanical polishing (CMP) to planarize a nonplanar submetal (or intermetal) silica dielectric layer. The planarized device is cleaned with an aqueous solution of ammonium hydroxide and citric acid. Exposed hydrated silica is etched using mixture of nitric and hydrofluoric acids, freeing embedded contaminants from the CMP slurry. The hydrofluroic acid is the etching agent, while the nitric acid combines with the freed contaminants to render water soluble products. They are thus carried away in an aqueous rinse, whereas otherwise they might recontaminate the device. A metal interconnect structure is formed on the etched oxide by forming contact apertures, depositing metal, and patterning the metal. The method can be applied also to nonplanar intermetal dielectrics and subsequent metal interconnect layers. The result is an integrated manufacturing method with higher yields and a more reliable manufactured integrated circuit.
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Craig A Bellows from San Antonio, TX, age ~76 Get Report