Cirillo Lino Costantino

7120728, Oct 10, 2006

Jul 31, 2002

10/209694

Shahe H. Krakirian - Palo Alto CA, US
Richard A. Walter - San Jose CA, US
Subbaro Arumilli - Santa Clara CA, US
Cirillo Lino Costantino - Oakland CA, US
L. Vincent M. Isip - Cupertino CA, US
Subhojit Roy - Sunnyvale CA, US
Naveen S. Maveli - Sunnyvale CA, US
Daniel Ji Yong Park Chung - San Jose CA, US
Stephen D. Elstad - San Jose CA, US
Dennis H. Makishima - Mountainview CA, US
Daniel Y. Chung - San Ramon CA, US

Brocade Communications Systems, Inc. - San Jose CA

G06F 12/00

711 6, 711206, 709244, 709245, 709249, 370379, 370382, 370386, 370399, 370422

Placing virtualization agents in the switches which comprise the SAN fabric. Higher level virtualization management functions are provided in an external management server. Conventional HBAs can be utilized in the hosts and storage units. In a first embodiment, a series of HBAs are provided in the switch unit. The HBAs connect to bridge chips and memory controllers to place the frame information in dedicated memory. Routine translation of known destinations is done by the HBA, based on a virtualization table provided by a virtualization CPU. If a frame is not in the table, it is provided to the dedicated RAM. Analysis and manipulation of the frame headers is then done by the CPU, with a new entry being made in the HBA table and the modified frames then redirected by the HBA into the fabric. This can be done in either a standalone switch environment or in combination with other switching components located in a director level switch. In an alternative embodiment, specialized hardware scans incoming frames and detects the virtualized frames which need to be redirected.

7269168, Sep 11, 2007

Jul 31, 2002

10/209742

Subhojit Roy - Sunnyvale CA, US
Richard A. Walter - San Jose CA, US
Cirillo Lino Costantino - Oakland CA, US
Naveen S. Maveli - Sunnyvale CA, US
Carlos Alonso - Los Gatos CA, US
Michael Yiu-Wing Pong - San Jose CA, US

Brocade Communications Systems, Inc. - San Jose CA

H04L 12/50
H04Q 11/00

370374, 370378, 370383, 370389, 370390, 3703957, 37039572, 370401, 370402, 711 6, 711111, 711114, 711144, 711145, 711203, 711205, 711208

Placing virtualization agents in the switches which comprise the SAN fabric. Higher level virtualization management functions are provided in an external management server. Conventional HBAs can be utilized in the hosts and storage units. In a first embodiment, a series of HBAs are provided in the switch unit. The HBAs connect to bridge chips and memory controllers to place the frame information in dedicated memory. Routine translation of known destinations is done by the HBA, based on a virtualization table provided by a virtualization CPU. If a frame is not in the table, it is provided to the dedicated RAM. Analysis and manipulation of the frame headers is then done by the CPU, with a new entry being made in the HBA table and the modified frames then redirected by the HBA into the fabric. This can be done in either a standalone switch environment or in combination with other switching components located in a director level switch. In an alternative embodiment, specialized hardware scans incoming frames and detects the virtualized frames which need to be redirected.

20040028043, Feb 12, 2004

Jul 31, 2002

10/209743

Naveen Maveli - Sunnyvale CA, US
Richard Walter - San Jose CA, US
Cirillo Costantino - Oakland CA, US
Subhojit Roy - Sunnyvale CA, US
Carlos Alonso - Los Gatos CA, US
Michael Pong - San Jose CA, US
Shahe Krakirian - Palo Alto CA, US
Subbarao Arumilli - Santa Clara CA, US
Vincent Isip - Cupertino CA, US
Daniel Chung - San Jose CA, US
Stephen Elstad - San Jose CA, US
Dennis Makishima - Mountainview CA, US

Brocade Communications Systems, Inc.

H04L012/28
H04L012/56

370/392000, 370/401000

Placing virtualization agents in the switches which comprise the SAN fabric. Higher level virtualization management functions are provided in an external management server. Conventional HBAs can be utilized in the hosts and storage units. In a first embodiment, a series of HBAs are provided in the switch unit. The HBAs connect to bridge chips and memory controllers to place the frame information in dedicated memory. Routine translation of known destinations is done by the HBA, based on a virtualization table provided by a virtualization CPU. If a frame is not in the table, it is provided to the dedicated RAM. Analysis and manipulation of the frame headers is then done by the CPU, with a new entry being made in the HBA table and the modified frames then redirected by the HBA into the fabric. This can be done in either a standalone switch environment or in combination with other switching components located in a director level switch. In an alternative embodiment, specialized hardware scans incoming frames and detects the virtualized frames which need to be redirected. The redirection is then handled by translation of the frame header information by hardware table-based logic and the translated frames are then returned to the fabric. Handling of frames not in the table and setup of hardware tables is done by an onboard CPU.

50365282, Jul 30, 1991

Jan 29, 1990

7/471915

Duc N. Le - Santa Clara CA
Lordson L. Yue - Sunnyvale CA
Cirillo L. Costantino - Castro Valley CA
David P. Chengson - Mountain View CA
Aurangzeb K. Khan - Cupertino CA

Tandem Computers Incorporated - Cupertino CA

H03D 324

375119

The present invention is directed to a self-calibrating clock synchronization system that receives a periodic, digital clock signal as a reference and generates therefrom a system clock signal that dynamically tracks and is synchronized to the reference clock. The invention utilizes state machine controlled selection circuitry that comprises a plurality of predetermined delays tapped to produce a number of phase-related clock signals, and multiplexing circuitry, for selecting one of the plurality of clock signals as the system clock. A comparator compares the selected clock signal and the reference clock to determine which leads or lags the other. In response to the comparison, selection, from the plurality of clock signals, of a system clock that most clearly matches the reference signal is made.

48004863, Jan 24, 1989

Sep 29, 1983

6/537877

Robert W. Horst - Cupertino CA
Shannon J. Lynch - Los Gatos CA
Cirillo L. Costantino - Castro Valley CA
John M. Beirne - Los Gatos CA

Tandem Computers Incorporated - Cupertino CA

G06F 928

364200

The various functional units which comprise a central processing unit of a computer are organized so as to enable a main arithmetic logic unit and special function units including an auxilliary arithmetic logic unit to access data registers, literal constants, and data from a memory cache. A general purpose bus closely couples the functional units to the main data paths and allows the CPU sequencer to branch on numerous conditions which may be indicated via test lines. Parity from the functional units is sent to clock cycle later than results in order that the parity path does not affect machine cycle time. The architecture allows unused microcode options to be used to check for correct CPU operation by halting CPU operation on a miscompare of two buses.

48232521, Apr 18, 1989

Feb 12, 1988

7/155427

Robert W. Horst - Cupertino CA
Cirillo L. Costantino - Castro Valley CA

Tandem Computers Incorporated - Cupertino CA

G06F 1120

371 8

An interleaved control store having a soft error recovery system. The system includes memory banks storing identical data sets, an error detection unit for indicating that an erroneous data element has been read from a given one of the memory banks, and a correction unit for substituting a corresponding data element read from another memory bank for the erroneous data element read from the given memory bank. Other embodiments include a feedback system for executing a branch and a dynamic, on-line memory element sparing system.

47543965, Jun 28, 1988

Mar 28, 1986

6/845738

Robert W. Horst - Cupertino CA
Cirillo L. Costantino - Castro Valley CA

Tandem Computers Incorporated - Cupertino CA

G06F 1100

364200

An overlapped control store including a pair of memory elements, with each element in the pair storing a complete instruction set and with instructions from the elements accessed on alternate clock cycles. A mux, controlled by a control field in each instruction, is adapted to provide either a PC address or a target address to the control store. Unrestricted branches are facilitated because every instruction in the instruction set is included in both memory elements.