Christy L Tyberg

6783862, Aug 31, 2004

Nov 8, 2002

10/290682

Jeffrey C Hedrick - Montvalle NJ
Kang-Wook Lee - Yorktown Heights NY
Kelly Malone - Poughkeepsie NY
Christy S Tyberg - Mahopac NY

International Business Machines Corporation - Armonk NY

B32B 904

428447, 428446, 428448, 257756, 257775, 438623, 438634, 438 6

A structure useful for electrical interconnection comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, tough, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. A method for forming the structure comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. Curing of the multilayer dielectric stack may be in a single cure step in a furnace. The application and hot plate baking of the individual layers of the multi layer dielectric stack may be accomplished in a single spin-coat tool, without being removed, to fully cure the stack until all dielectric layers have been deposited.

6818285, Nov 16, 2004

Dec 31, 2002

10/334413

Jeffrey C. Hedrick - Montvale NJ
Muthumanickam Sankarapandian - Yorktown Heights NY
Christy S. Tyberg - Mahopac NY
James P. Godschalx - Midland MI
Qingshan J. Niu - Midland MI
Harry C. Silvis - Midland MI

International Business Machines Corporation - Armonk NY

B32B 310

428209, 4284111, 428901, 526281, 526283, 526285

A crosslinked polyarylene material with a reduced coefficient of thermal expansion at high temperatures compared with conventional crosslinked polyarylene materials is provided. In addition, an integrated circuit article containing a crosslinked polyarylene polymer with reduced coefficient of thermal expansion at high temperatures is provided.

6844257, Jan 18, 2005

Jun 23, 2003

10/601387

Ann R Fornof - Blacksburg VA, US
Jeffrey C Hedrick - Montvalle NJ, US
Kang-Wook Lee - Yorktown Heights NY, US
Christy S Tyberg - Mahopac NY, US

International Business Machines Corporation - Armonk NY

H01L 214763

438634, 438628, 438622

An electrical interconnect structure on a substrate, includes a first porous dielectric layer with surface region from which a porogen has been removed; and an etch stop layer disposed upon the first porous dielectric layer so that the etch stop layer extends to partially fill pores in the surface region of the first porous dielectric layer from which the porogen has been removed, thus improving adhesion during subsequent processing. The porogen may be removed from the surface region by heating, and in particular by hot plate baking. A second porous dielectric layer, which may have the same composition as the first porous dielectric layer, may be formed over the etch stop layer. Electrical vias and lines may be formed in the first and second porous dielectric layer, respectively. The layers may be part of a multilayer stack, wherein all of the layers are cured simultaneously in a spin application tool porous dielectric layer.

6933586, Aug 23, 2005

Nov 8, 2002

10/290616

Ann R Fornof - Blacksburg VA, US
Jeffrey C Hedrick - Montvalle NJ, US
Kang-Wook Lee - Yorktown Heights NY, US
Christy S Tyberg - Mahopac NY, US

International Business Machines Corporation - Armonk NY

H01L029/00

257508, 257506, 257507, 257524

An electrical interconnect structure on a substrate, includes a first porous dielectric layer with surface region from which a porogen has been removed; and an etch stop layer disposed upon the first porous dielectric layer so that the etch stop layer extends to partially fill pores in the surface region of the first porous dielectric layer from which the porogen has been removed, thus improving adhesion during subsequent processing. The porogen may be removed from the surface region by heating, and in particular by hot plate baking. A second porous dielectric layer, which may have the same composition as the first porous dielectric layer, may be formed over the etch stop layer. Electrical vias and lines may be formed in the first and second porous dielectric layer, respectively. The layers may be part of a multilayer stack, wherein all of the layers are cured simultaneously in a spin application tool porous dielectric layer.

7057287, Jun 6, 2006

Aug 21, 2003

10/645308

Kaushik A Kumar - Beacon NY, US
Kelly Malone - Poughkeepsie NY, US
Christy S Tyberg - Mahopac NY, US

International Business Machines Corporation - Armonk NY

H01L 23/48
H01L 23/52
H01L 29/40

257758, 257774

A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

7071539, Jul 4, 2006

Jul 28, 2003

10/628925

Lee M Nicholson - Katonah NY, US
Wei-Tsu Tseng - Hopewell Junction NY, US
Christy S Tyberg - Mahopac NY, US

International Business Machines Corporation - Armonk NY

H01L 23/58
H01L 23/48

257642, 257643, 257759, 257760

An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

7084479, Aug 1, 2006

Dec 8, 2003

10/731377

Stefanie Ruth Chiras - Peekskill NY, US
Matthew Earl Colburn - Hopewell Junction NY, US
Timothy Joseph Dalton - Ridgefield CT, US
Jeffrey Curtis Hedrick - Montvale NJ, US
Elbert Emin Huang - Tarrytown NY, US
Kaushik Arun Kumar - Beacon NY, US
Michael Wayne Lane - Cortlandt Manor NY, US
Kelly Malone - Poughkeepsie NY, US
Chandrasekhar Narayan - Hopewell Junction NY, US
Satyanarayana Venkata Nitta - Poughquag NY, US
Sampath Purushothaman - Yorktown Heights NY, US
Robert Rosenburg - Cortlandt Manor NY, US
Christy Sensenich Tyberg - Mahopac NY, US
Roy RongQing Yu - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

H01L 29/00
H01L 23/48
H01L 23/52
H01L 29/40

257522, 257758, 257 21581, 257 21573, 257 23013

In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

7187081, Mar 6, 2007

Oct 31, 2003

10/699238

Elbert E. Huang - Tarrytown NY, US
Kaushik A. Kumar - Beacon NY, US
Kelly Malone - Poughkeepsie NY, US
Dirk Pfeiffer - Dobbs Ferry NY, US
Muthumanickam Sankarapandian - Yorktown Heights NY, US
Christy S. Tyberg - Mahopac NY, US

International Business Machines Corporation - Armonk NY

H01L 29/40

257759, 257774, 438970

Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SiNCOH, where 0. 05≦v≦0. 8, 0≦w≦0. 9, 0. 05≦x≦0. 8, 0≦y≦0. 3, 0. 05≦z≦0. 8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.