Christopher A Lane

6366121, Apr 2, 2002

May 25, 2001

09/865227

Richard G. Cliff - Milpitas CA
Francis B. Heile - Santa Clara CA
Joseph Huang - San Jose CA
Christopher F. Lane - Campbell CA
Fung Fung Lee - Milpitas CA
Cameron McClintock - Mountain View CA
David W. Mendel - Sunnyvale CA
Ninh D. Ngo - San Jose CA
Bruce B. Pedersen - San Jose CA
Srinivas T. Reddy - Fremont CA
Chiakang Sung - Milpitas CA
Kerry Veenstra - San Jose CA
Bonnie I. Wang - Cupertino CA

Altera Corporation - San Jose CA

G06F 738

326 41, 326 39

A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e. g. , by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate âlonely registerâ function in modules of the regions.

6373280, Apr 16, 2002

Feb 28, 2001

09/795796

Christopher F. Lane - Campbell CA
Srinivas T. Reddy - Fremont CA

Altera Corporation - San Jose CA

A03K 19177

326 41, 326 38

A programmable logic integrated circuit device has a plurality of areas of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such areas. A so-called âfast conductorâ network is provided on the device for rapidly and efficiently distributing a relatively small number of signals to substantially any logic area on the device. The fast conductor network has several main conductors that substantially bisect the array in one direction (e. g. , by extending parallel to the column axis). Some main conductors can carry signals from off the device. Other main conductors can carry signals generated on the device. The network further includes secondary conductors that extend transverse to the main conductors (e. g. , along each row of logic areas). Programmable logic connectors are provided for selectively applying signals from the main conductors to the secondary conductors and from the secondary conductors to the logic areas.

6384625, May 7, 2002

Mar 30, 2001

09/823603

Andy L. Lee - San Jose CA
Christopher F. Lane - Campbell CA
Bruce B. Pedersen - San Jose CA

Altera Corporation - San Jose CA

G06F 738

326 38, 326 39, 326 41

Programmable logic modules on a programmable logic device each include a four-input look-up table circuit which can be programmed to allow the logic module to produce an output signal which can be any of a plurality of logical combinations of four input signals applied to the logic module. In addition, each logic module is augmented with additional circuitry that allows the logic module to be alternatively operated as a dynamic four-to-one multiplexer.

6392438, May 21, 2002

Oct 6, 2000

09/684148

Richard G. Cliff - Milpitas CA
Srinivas T. Reddy - Santa Clara CA
David Edward Jefferson - San Jose CA
Rina Raman - Fremont CA
L. Todd Cope - San Jose CA
Christopher F. Lane - Campbell CA
Joseph Huang - San Jose CA
Francis B. Heile - Santa Clara CA
Bruce B. Pedersen - San Jose CA
David Wolk Mendel - Sunnyvale CA
Craig Schilling Lytle - Mountain View CA
Robert Richard Noel Bielby - Pleasonton CA
Kerry Veenstra - San Jose CA

Altera Corporation - San Jose CA

H03K 1977

326 41, 326 39

A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

6418874, Jul 16, 2002

May 25, 2000

09/584167

Michael S. Cox - Davenport CA
Canfeng Lai - Fremont CA
Robert B. Majewski - Felton CA
David P. Wanamaker - San Jose CA
Christopher T. Lane - San Jose CA
Peter Loewenhardt - San Jose CA
Shamouil Shamouilian - San Jose CA
John P. Parks - San Jose CA

Applied Materials, Inc. - Santa Clara CA

C23C 1600

118723I, 118723 IR, 156345, 31511151, 31511171

A toroidal plasma source ( ) within a substrate processing chamber ( ). The toroidal plasma source forms a poloidal plasma with theta symmetry. The poloidal plasma current is essentially parallel to a surface of the plasma generating structure, thus reducing sputtering erosion of the inner walls. The plasma current is similarly essentially parallel to a process surface ( ) of a substrate ( ) within the chamber. In a further embodiment, a shaped member ( ) between the substrate and the plasma source controls the plasma density in a selected fashion to enhance plasma processing uniformity.

6462577, Oct 8, 2002

Jan 16, 2001

09/761608

Andy L. Lee - San Jose CA
Christopher F. Lane - San Jose CA
Srinivas T. Reddy - Fremont CA
Brian D. Johnson - Sunnyvale CA
Ketan H. Zaveri - San Jose CA
Mario Guzman - San Jose CA
Quyen Doan - Milpitas CA

Altera Corporation - San Jose CA

H03K 19177

326 40, 326 47

A programmable logic device is provided in which logic array blocks (LABs) may be programmably configured for use as one of a variety of memory structures. The configurable memory structures may have separate read and write addresses, thereby making it possible to implement a variety of memory structures such as FIFO memory, ROM, RAM, and shift-registers.

6480028, Nov 12, 2002

Feb 1, 2002

10/062741

David E. Jefferson - San Jose CA
Cameron McClintock - Mountain View CA
James Schleicher - Santa Clara CA
Andy L. Lee - San Jose CA
Manuel Mejia - San Jose CA
Bruce B. Pederson - San Jose CA
Christopher F. Lane - Campbell CA
Richard G. Cliff - Milpitas CA
Srinivas T. Reddy - Fremont CA

Altera Corporation - San Jose CA

H03K 19177

326 41, 326 40

A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.

6481000, Nov 12, 2002

Jun 29, 2000

09/608061

Ketan Zaveri - San Jose CA
Christopher F. Lane - Campbell CA
Srinivas T. Reddy - Fremont CA
Andy L. Lee - San Jose CA
Cameron R. McClintock - Mountain View CA
Bruce B. Pedersen - San Jose CA

Altera Corporation - San Jose CA

G06F 1750

716 17, 326 39, 716 2, 716 4, 716 16, 716 18

A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device. Circuitry is also provided that may be used for preloading data into various circuits on the device. The logic signal observing circuitry may allow registered signals to be observed, may allow combinatorial signals to be observed, or may allow both registered and combinatorial signals to be observed.