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Christophe A Hurni

from Seattle, WA
Age ~40
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Also known as:
Christopher Hurni
Connected to:
Phillip R Hurni, 64Lisa Hurns, 57Renard K Hurns, 58Dana J Huron, 34Genevieve M Huron, 38Kevin J Huron, 53Lisa Huron, 31Matthew J Huron, 59Rhondie L Huron, 54Robert A Huron, 62

Christophe Hurni Phones & Addresses

  • Seattle, WA
  • Oakland, CA
  • San Leandro, CA
  • Santa Barbara, CA
  • Fremont, CA

Work

Company: Soraa Sep 2012 Address: Bay Area, CA Position: Device scientist

Education

Degree: Doctor of Philosophy (PhD) School / High School: University of California, Santa Barbara 2007 to 2012 Specialities: GaN, Semiconductor Physics, Growth, Processing

Skills

Materials Science • Thin Films • Characterization • Physics • Device Characterization • Epitaxy • Semiconductor Process • Semiconductor Device • Process Integration • Afm • Nanofabrication • Design of Experiments • Optoelectronics • Comsol • Photonics • Scanning Electron Microscopy • Microfabrication • Nanotechnology • Powder X Ray Diffraction • Photolithography • Cvd • Nanomaterials • Semiconductors • Laser • Optics

Languages

English • French • German

Industries

Electrical/Electronic Manufacturing

Resumes

Resumes

Christophe Hurni Photo 1

Scientist At Facebook Reality Labs

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Location:
Oakland, CA
Industry:
Electrical/Electronic Manufacturing
Work:
Soraa - Bay Area, CA since Sep 2012
Device Scientist
UC Santa Barbara Sep 2007 - Oct 2012
PhD candidate
University of California Mar 2009 - Jun 2009
Teaching Assistant
TU-Wien Apr 2007 - Jul 2007
Research scientist
EPFL 2006 - 2007
Master Student
Education:
University of California, Santa Barbara 2007 - 2012
Doctor of Philosophy (PhD), GaN, Semiconductor Physics, Growth, Processing Ecole polytechnique fédérale de Lausanne 2002 - 2007
B.Sc. and M.Sc., Physics Swiss Federal Institute of Technology (EPFL) 2002 - 2007
Master of Science (MSc), Physics Technische Universität Wien 2004 - 2005
Erasmus exchange program, Physics Lycee Denis de Rougemont 1999 - 2002
BAC
Skills:
Materials Science
Thin Films
Characterization
Physics
Device Characterization
Epitaxy
Semiconductor Process
Semiconductor Device
Process Integration
Afm
Nanofabrication
Design of Experiments
Optoelectronics
Comsol
Photonics
Scanning Electron Microscopy
Microfabrication
Nanotechnology
Powder X Ray Diffraction
Photolithography
Cvd
Nanomaterials
Semiconductors
Laser
Optics
Languages:
English
French
German

Publications

Us Patents

Selective Dry Etching Of N-Face (Al,In,Ga)N Heterostructures

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US Patent:
20130099277, Apr 25, 2013
Filed:
Oct 25, 2012
Appl. No.:
13/660782
Inventors:
The Regents of the University of California - Oakland CA, US
Evelyn L. Hu - Cambridge MA, US
Claude C.A. Weisbuch - Paris, FR
Yong Seok Choi - Goleta CA, US
Michael Iza - Goleta CA, US
Christophe Hurni - Goleta CA, US
Assignee:
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA - Oakland CA
International Classification:
H01L 33/02
H01L 21/306
H01L 29/20
US Classification:
257101, 438 37, 257615, 438706, 257E33023, 257E29089, 257E21222
Abstract:
A method of selective dry etching of N-face (Al,In,Ga)N heterostructures through the incorporation of an etch-stop layer into the structure, and a controlled, highly selective, etch process. Specifically, the method includes: (1) the incorporation of an easily formed, compatible etch-stop layer in the growth of the device structure, (2) the use of a laser-lift off or similar process to decouple the active layer from the original growth substrate, and (3) the achievement of etch selectivity higher than 14:1 on N-face (Al,In,Ga)N.

Current Aperture Vertical Electron Transistors With Ammonia Molecular Beam Epitaxy Grown P-Type Gallium Nitride As A Current Blocking Layer

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US Patent:
20120319127, Dec 20, 2012
Filed:
Jun 20, 2012
Appl. No.:
13/527885
Inventors:
Srabanti Chowdhury - Goleta CA, US
Ramya Yeluri - Santa Barbara CA, US
Christophe Hurni - Goleta CA, US
Umesh K. Mishra - Montecito CA, US
Ilan Ben-Yaacov - Goleta CA, US
Assignee:
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA - Oakland CA
International Classification:
H01L 29/20
H01L 21/20
US Classification:
257 76, 438478, 257E29089, 257E2109
Abstract:
A current aperture vertical electron transistor (CAVET) with ammonia (NH) based molecular beam epitaxy (MBE) grown p-type Gallium Nitride (p-GaN) as a current blocking layer (CBL). Specifically, the CAVET features an active buried Magnesium (Mg) doped GaN layer for current blocking purposes. This structure is very advantageous for high power switching applications and for any device that requires a buried active p-GaN layer for its functionality.

Rendering Images On Displays

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US Patent:
20210383771, Dec 9, 2021
Filed:
Jun 3, 2020
Appl. No.:
16/891908
Inventors:
- Menlo Park CA, US
Gareth Valentine - Redmond WA, US
Christophe Antoine Hurni - Seattle WA, US
James Ronald Bonar - Redmond WA, US
International Classification:
G09G 5/04
G06T 11/00
G09G 5/10
Abstract:
In one embodiment, a computing system may receive a target color and a propagated error for a pixel location. The system may determine an error-modified target color for the pixel location based on the received target color and the propagated error. The system may identify, based on a location of the error-modified target color in a three-dimensional color space, a subset of pre-determined colors in the three-dimensional color space. The error-modified target color may correspond to a weighted combination of the subset of pre-determined colors. The system may determine a pixel color for the pixel location based on the subset of pre-determined colors and respective weights associated with the subset of pre-determined colors. The system may determine, based on the pixel color, driving signals for light-emitting elements associated with the pixel location. The system may output the driving signals to control the light-emitting elements associated with the pixel location.

Digital Projector For Local Dimming In A Device

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US Patent:
20210325696, Oct 21, 2021
Filed:
Apr 15, 2020
Appl. No.:
16/849859
Inventors:
- Menlo Park CA, US
JASMINE SORIA SEARS - Kirkland WA, US
CHRISTOPHE ANTOINE HURNI - Seattle WA, US
NATHAN MATSUDA - Seattle WA, US
GUOHUA WEI - Redmond WA, US
Yu Shi - Redmond WA, US
John Goward - Redmond WA, US
International Classification:
G02C 7/10
G02B 27/01
G02B 27/42
G02B 5/26
Abstract:
A device includes an optical assembly and a digital projector. The optical assembly is configured to receive visible scene light at a backside of the optical assembly and to direct the visible scene light on an optical path toward an eyeward side. The optical assembly includes a dimming layer disposed on the optical path. The dimming layer includes a photochromic material that is configured to darken in response to exposure to a range of light wavelengths. The digital projector is disposed on the eyeward side of the optical assembly and is configured to selectively emit an activation light within the range of light wavelengths to activate a darkening of a region of the dimming layer to dim the visible scene light within the region.

Local Dimming In A Device

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US Patent:
20210325699, Oct 21, 2021
Filed:
Apr 15, 2020
Appl. No.:
16/849853
Inventors:
- Menlo Park CA, US
JASMINE SORIA SEARS - Kirkland WA, US
CHRISTOPHE ANTOINE HURNI - Seattle WA, US
NATHAN MATSUDA - Seattle WA, US
GUOHUA WEI - Redmond WA, US
YU SHI - Redmond WA, US
JOHN GOWARD - Redmond WA, US
International Classification:
G02F 1/01
G02B 27/01
G09G 5/10
Abstract:
An optical assembly is configured to receive visible scene light at a backside of the optical assembly and to direct the visible scene light on an optical path toward the eyeward side. The optical assembly also includes a dimming layer disposed on the optical path, where the dimming layer includes a photochromic material that is configured to darken in response to exposure to a range of light wavelengths. An activation layer, included in the optical assembly, is also disposed on the optical path and includes an in-field dimmer. The in-field dimmer is configured to selectively emit an activation light within the range of light wavelengths to activate a darkening of a region of the dimming layer to dim the visible scene light within the region.

High-Performance Led Fabrication

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US Patent:
20210050480, Feb 18, 2021
Filed:
Jun 22, 2020
Appl. No.:
16/907650
Inventors:
- Los Angeles CA, US
Aurelien J.F. David - San Francisco CA, US
Christophe Hurni - Fremont CA, US
Rafael Aldaz - Pleasanton CA, US
Michael Ragan Krames - Mountain View CA, US
International Classification:
H01L 33/32
H01L 33/60
F21V 29/70
H01L 33/02
H01L 33/16
H01L 33/20
H01L 33/40
H01L 33/48
H01L 33/62
Abstract:
High-performance light-emitting diode together with apparatus and method embodiments thereto are disclosed. The light emitting diode devices emit at a wavelength of 390 nm to 470 nm or at a wavelength of 405 nm to 430 nm. Light emitting diode devices are characterized by having a geometric relationship (e.g., aspect ratio) between a lateral dimension of the device and a vertical dimension of the device such that the geometric aspect ratio forms a volumetric light emitting diode that delivers a substantially flat current density across the device (e.g., as measured across a lateral dimension of the active region). The light emitting diode devices are characterized by having a current density in the active region of greater than about 175 Amps/cm.

High Efficiency Group-Iii Nitride Light Emitting Diode

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US Patent:
20190386178, Dec 19, 2019
Filed:
Jun 19, 2019
Appl. No.:
16/446022
Inventors:
- Fremont CA, US
CHRISTOPHE HURNI - FREMONT CA, US
NATHAN YOUNG - FREMONT CA, US
International Classification:
H01L 33/32
H01L 33/06
Abstract:
A method of improving high-current density efficiency of an LED, said method comprising: (a) preparing a series of LEDs having decreasing defect densities, wherein each LED of said series has a peak IQE of at least 50%, and wherein each LED of said series has the same epitaxial structure; (b) determining an increase in IQEs at high-current density between at least two LEDs of said series; (c) preparing at least an additional LED of said series by reducing defect density relative to the previously obtained lowest defect density; and (d) reiterating steps (b) and (c) until said increase is at least 3% between two LEDs of said series having a decrease X in defect densities.

High-Performance Led Fabrication

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US Patent:
20190165212, May 30, 2019
Filed:
Oct 23, 2018
Appl. No.:
16/168311
Inventors:
- Fremont CA, US
Aurelien J.F. David - San Francisco CA, US
Christophe Hurni - Fremont CA, US
Rafael Aldaz - Pleasanton CA, US
Michael Ragan Krames - Mountain View CA, US
International Classification:
H01L 33/32
H01L 33/40
F21V 29/70
H01L 33/20
H01L 33/16
H01L 33/48
H01L 33/60
H01L 33/62
H01L 33/02
Abstract:
High-performance light-emitting diode together with apparatus and method embodiments thereto are disclosed. The light emitting diode devices emit at a wavelength of 390 nm to 470 nm or at a wavelength of 405 nm to 430 nm. Light emitting diode devices are characterized by having a geometric relationship (e.g., aspect ratio) between a lateral dimension of the device and a vertical dimension of the device such that the geometric aspect ratio forms a volumetric light emitting diode that delivers a substantially flat current density across the device (e.g., as measured across a lateral dimension of the active region). The light emitting diode devices are characterized by having a current density in the active region of greater than about 175 Amps/cm.
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Christophe A Hurni from Seattle, WA, age ~40 Get Report