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Christian Warling Phones & Addresses

  • 4155 Valley Oak Dr, Loveland, CO 80538 (970) 461-8587
  • 1384 4Th St, Loveland, CO 80537
  • Fort Collins, CO
  • Roseville, CA
  • Rocklin, CA

Publications

Us Patents

Logic Output Circuit With High Transient Pull-Up Current

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US Patent:
54444004, Aug 22, 1995
Filed:
Nov 2, 1993
Appl. No.:
8/146254
Inventors:
Steven G. Hall - Fort Collins CO
Lawrence N. Taugher - Fort Collins CO
Kerry J. Monroe - Fort Collins CO
Christian J. Warling - Loveland CO
Thomas L. Bloom - Loveland CO
William P. Repasky - Fort Collins CO
Erik R. Habbinga - Longmont CO
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
H03K 1704
US Classification:
327108
Abstract:
A digital line driver circuit with active pull-down, high transient pull-up current, and limited steady-state pull-up current. Steady-state pull-up current is provided through a pull-up resistor. Transient pull-up current is provided by a capacitively coupled active pull-up circuit.

Hardware Checksum Assist For Network Protocol Stacks

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US Patent:
62890239, Sep 11, 2001
Filed:
Sep 25, 1997
Appl. No.:
8/937912
Inventors:
Brian M. Dowling - El Dorado Hills CA
Christian J. Warling - Rocklin CA
James G. Wendt - Auburn CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
H04L 1228
US Classification:
370419
Abstract:
A fly-by checksum is generated at a lower layer of the protocol stack and travels up to a high layer of a protocol stack to verify incoming data. In one embodiment, a network adapter comprises includes one or more protocol stacks and a LAN controller that includes a fly-by checksum generation unit. A checksum algorithm is registered with the fly-by checksum generation unit for each protocol layer that is to receive a fly-by checksum. As an incoming packet is transferred from network media to network adapter memory, the fly-by checksum generation unit calculates a fly-by checksum for each checksum algorithm that has been registered. After the fly-by checksums are complete, they are transmitted to the network adapter memory and are transmitted up the appropriate protocol stack within a checksum channel. When data reaches a layer of the protocol stack for which the fly-by checksum was generated, the fly-by checksum is removed from the checksum channel and is used to verify the integrity of the data.

Media Access Controller Capable Of Connecting To A Serial Physical Layer Device And A Media Independent Interface (Mii) Physical Layer Device

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US Patent:
62755013, Aug 14, 2001
Filed:
Apr 21, 1998
Appl. No.:
9/063686
Inventors:
Mark C. Lucas - Auburn CA
Eric McLaughlin - Grass Valley CA
Christian Warling - Rocklin CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
H04L 1226
US Classification:
370463
Abstract:
A network node includes a serial physical sublayer (PHY) chip, a parallel PHY chip, and a media access control (MAC) chip. The serial physical sublayer chip, includes a single bit transmit data input, a single bit receive data output, and serial PHY control signal input/output (I/O) lines. The parallel PHY chip includes a multi-bit transmit data input, a multi-bit receive data output, and parallel PHY control signal I/O lines. The MAC chip includes a multi-bit transmit data output, a multi-bit receive data input and parallel control signal I/O lines. The multi-bit transmit data output is connected to the multi-bit transmit data input. One bit of the multi-bit transmit data output is connected to the single bit transmit data input. The multi-bit receive data input is connected to the multi-bit receive data output. One bit of the multi-bit receive data input is connected to the single bit receive data output.

Debug Apparatus And Methods For Dynamically Switching Power Domains

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US Patent:
20150082092, Mar 19, 2015
Filed:
Sep 16, 2013
Appl. No.:
14/027711
Inventors:
- Sunnyvale CA, US
Christian Warling - Loveland CO, US
Eric Rentschler - Ft. Collins CO, US
Vikram Chopra - Fremont CA, US
Mihir Doctor - Sunnyvale CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 11/27
G01R 31/317
US Classification:
714 30
Abstract:
Methods and apparatus are provided that facilitate debugging operations for components that may include different power domains. In an embodiment, an integrated circuit (IC) includes a plurality of hardware sectors, each hardware sector associated with a debug observability circuit that is served by a debug data bus of a debug circuit. The plurality of hardware sectors includes a controlled sector residing in a dynamically-controlled power domain that may be turned off while the power domain of another sector remains on. A selectively switchable data bus component is configured to couple the debug observability circuit associated with the controlled sector to the debug data bus when the power to the controlled sector is on and to switch to bypass the debug observability circuit associated with the controlled sector when the power to the controlled sector is not on.
Christian J Warling from Loveland, CO, age ~58 Get Report