Chris J Lane

6605962, Aug 12, 2003

Jan 25, 2002

10/057442

Andy L. Lee - San Jose CA
Cameron McClintock - Mountain View CA
Brian Johnson - Sunnyvale CA
Richard Cliff - Los Altos CA
Srinivas Reddy - Fremont CA
Chris Lane - San Jose CA
Paul Leventis - Toronto, CA
Vaughn Timothy Betz - Toronto, CA
David Lewis - Toronto, CA

Altera Corporation - San Jose CA

H03K 19177

326 41, 326 38, 326 39, 716 1, 716 16, 716 17

In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

7058920, Jun 6, 2006

Jun 11, 2003

10/460685

Andy L. Lee - San Jose CA, US
Cameron McClintock - Mountain View CA, US
Brian Johnson - Sunnyvale CA, US
Richard Cliff - Los Altos CA, US
Srinivas Reddy - Fremont CA, US
Chris Lane - San Jose CA, US
Paul Leventis - Toronto, CA
Vaughn Timothy Betz - Toronto, CA
David Lewis - Toronto, CA

Altera Corporation - San Jose CA

G06F 17/50

716 16, 716 10, 716 12, 716 17, 326 39, 326 40, 326 41

In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

7112992, Sep 26, 2006

Dec 8, 2004

11/008080

Mario Guzman - San Jose CA, US
Chris Lane - San Jose CA, US
Andy L. Lee - San Jose CA, US
Ninh Ngo - San Jose CA, US

Altera Corporation - San Jose CA

H03K 19/173

326 38, 326 39, 326 41

An electronic device comprises a first plurality of configuration elements connected as a shift register for programming a subset of the programmable functions of the electronic device. The subset of programmable functions may be reprogrammed by loading configuration data into the first plurality of configuration elements such that the subset of programmable functions may be reprogrammed without necessarily reprogramming other programmable functions of the electronic device.

7180324, Feb 20, 2007

May 28, 2004

10/856434

Michael Chan - Scarborough, CA
Paul Leventis - Toronto, CA
David Lewis - Toronto, CA
Ketan Zaveri - San Jose CA, US
Hyun Mo Yi - Mountain View CA, US
Chris Lane - San Jose CA, US

Altera Corporation - San Jose CA

H03K 19/003

326 10, 326 9, 326 41

An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.

7253660, Aug 7, 2007

Nov 27, 2002

10/305886

Paul Leventis - Toronto, CA
Bruce Pedersen - San Jose CA, US
Chris Lane - San Jose CA, US
Srinivas Reddy - Fremont CA, US
David Lewis - Toronto, CA

Altera Corporation - San Jose CA

H01L 25/00
H03K 19/177

326 41, 326 37, 326 47, 326113

A multiplexing device is described. In one embodiment, the multiplexing device includes: a hardwired multiplexer including a plurality of input terminals; a plurality of select terminals; and at least one output terminal, where the plurality of input terminals are coupled to a plurality of block input lines or a plurality of functional element input terminals. In one embodiment, the plurality of input terminals are hardwired to the plurality of block input lines or the plurality of functional element input terminals. In one embodiment, the plurality of select terminals are coupled to a second plurality of functional element input terminals or a plurality of functional element output terminals. In one embodiment, the plurality of block input lines include a plurality of logic array block (LAB) lines, the plurality of functional element input terminals include a plurality of logic element (LE) input terminals, and the plurality of functional element output terminals include LE output terminals. In another embodiment the multiplexing device includes: a hardwired multiplexer including a plurality of data signal input terminals; and a first plurality of LEs including a first plurality of LE output terminals, where the plurality of data signal input terminals are coupled to the first plurality of LE output terminals.

7584447, Sep 1, 2009

Aug 12, 2005

11/202616

Andy L. Lee - San Jose CA, US
Cameron McClintock - Mountain View CA, US
Brian Johnson - Sunnyvale CA, US
Richard Cliff - Los Altos CA, US
Srinivas Reddy - Fremont CA, US
Chris Lane - San Jose CA, US
Paul Leventis - Toronto, CA
Vaughn Timothy Betz - Toronto, CA
David Lewis - Toronto, CA

Altera Corporation - San Jose CA

G06F 17/50
H03K 19/177

716 16, 716 1, 716 10, 716 12, 716 17, 326 39, 326 40, 326 41

In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

7644386, Jan 5, 2010

Jan 17, 2007

11/623903

Michael Chan - Ontario, CA
Paul Leventis - Ontario, CA
David Lewis - Ontario, CA
Ketan Zaveri - San Jose CA, US
Hyun Mo Yi - Mountain View CA, US
Chris Lane - San Jose CA, US

Altera Corporation - San Jose CA

G06F 17/50

716 16, 716 18

An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.

8191025, May 29, 2012

Sep 1, 2009

12/552214

Michael Chan - Scarborough, CA
Paul Leventis - Toronto, CA
David Lewis - Toronto, CA
Ketan Zaveri - San Jose CA, US
Hyun Mo Yi - Mountain View CA, US
Chris Lane - San Jose CA, US

Altera Corporation - San Jose CA

G06F 17/50
G06F 9/00
G06F 15/177
H03K 19/00
H01L 25/00

716117, 716121, 716128, 326 38, 326 41, 326 47, 326101, 713 1, 713 2, 713100

An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.