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Chia-Jen Chang Phones & Addresses

  • Cupertino, CA

Publications

Us Patents

Redundancy Programming Circuit And System For Semiconductor Memory

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US Patent:
58986260, Apr 27, 1999
Filed:
Jun 19, 1997
Appl. No.:
8/879208
Inventors:
Paul M-Bhor Chiang - Santa Clara CA
Hung-Mao Lin - Santa Clara CA
Chia-Jen Chang - Santa Clara CA
Assignee:
Silicon Magic Corporation - Santa Clara CA
International Classification:
G11C 700
US Classification:
365200
Abstract:
Circuit, method, and system aspects for achieving redundancy circuitry programming in semiconductor memory are provided. Through these aspects, utilization of a circuit including a logic mechanism for receiving an enable signal and an address signal, a switching mechanism coupled to the logic mechanism for controlling delivery of the address signal, and a fuse mechanism coupled to the logic mechanism for allowing selective address programming responsive to the address signal in order to produce a desired logic level for a redundant address output signal occurs to form an address programming circuit. Further, selective input of an enable signal to the address programming circuit provides control of the address programming circuit to produce a desired logic level output. Additionally, integration of a plurality of the address programming circuits to form a redundancy programming circuit is achieved with each address programming circuit corresponding to one bit of an input address signal.

Self-Bootstrapping Word-Line Driver Circuit And Method

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US Patent:
60257512, Feb 15, 2000
Filed:
Oct 8, 1997
Appl. No.:
8/947754
Inventors:
Paul M-Bhor Chiang - Cupertino CA
Chia-Jen Chang - San Jose CA
Hung-Mao Lin - San Jose CA
Rita Au Hsu - San Jose CA
Assignee:
Silicon Magic Corporation - Santa Clara CA
International Classification:
H03M 7162
US Classification:
327589
Abstract:
Aspects for self bootstrapping word-line driver circuitry are provided. In a circuit aspect, a word-line driver circuit for a memory cell in a semiconductor memory includes a signal input means, the signal input means comprising a first plurality of transistors, the first plurality of transistors receiving an input voltage signal higher than a voltage supply signal of the semiconductor memory. The circuit further includes a signal output means, the signal output means comprising a second plurality of transistors coupled to the first plurality of transistors and providing an output drive signal sufficient for the memory cell. In a method aspect, a method for providing proper voltage level output of a word-line driver circuit for a semiconductor memory includes forming a self-bootstrap circuit as the word-line driver circuit and providing an input voltage signal to the self-bootstrap circuit, the input voltage signal acting as a source voltage for the circuit and being higher by a predetermined value than a supply voltage of the semiconductor memory.
Chia-Jen J Chang from Cupertino, CA Get Report