Chi Chan Cheng from Fremont, CA, age 55

Resumes

Office Manager

View page

Work:

Smart Hua
Office Manager

Chi Cheng

View page

Chi Cheng

View page

Software Engineer At Nvidia

View page

Location:

San Francisco Bay Area

Industry:

Computer Hardware

Student At Academy Of Art University

View page

Location:

San Francisco Bay Area

Industry:

Music

Chi Cheng

View page

Business Records

Name / Title

Company / Classification

Phones & Addresses

Chi Cheng
President

CHINESE SENIORS UNITED ASSOCIATION OF NORTHERN CALIFORNIA
Membership Organization

20817 Hillmore Dr, Saratoga, CA 95070
10252 Parlett Pl, Cupertino, CA 95014
3301 Ingersoll Ct, San Jose, CA 95148

Chi Wai Cheng
President

Vc Accessories, Inc

3720 Loma Vis Ave, Oakland, CA 94619

Chi Cheng
President

CHENG'S ENTERPRISES, INC

3301 Ingersoll Ct, San Jose, CA 95148

Chi Cheng
M

Goldlink, LLC

Chi Yin Cheng
Director, Secretary

World Buffet Co
Eating Place

76 Copper Fountain St, Las Vegas, NV 89138
24 Perth Pl, Berkeley, CA 94705
2131 Rock Spg Dr, Las Vegas, NV 89128
5507 Pt Lobos Ct, Union City, CA 94587

Publications

Us Patents

High Speed Inductor Current Driver With Minimum Overshoot

View page

US Patent:

6429987, Aug 6, 2002

Filed:

Apr 10, 2000

Appl. No.:

09/546039

Inventors:

Chi Fung Cheng - San Jose CA

Assignee:

Marvell International, Inc. - Hamilton

International Classification:

G11B 509

US Classification:

360 46, 46360, 46 68

Abstract:

A high speed write driver for an inductive head of a magnetic storage medium is provided which contains a mechanism to reduce the inductive head current overshoot and therefore reduce jitter and, thus, increase the write cycle frequency. An input voltage control stage controls a voltage applied to the inductive head from the voltage source. A current supply to supplies current to the inductive head element, and a damping circuit in communication with the inductive head element. An overshoot suppressor circuit is provided such that the input voltage control tage is responsive to the overshoot suppressor circuit.

Precompensation Circuit For Magnetic Recording

View page

US Patent:

6721114, Apr 13, 2004

Filed:

Jun 5, 2001

Appl. No.:

09/874949

Inventors:

Pantas Sutardja - San Jose CA
Chi Fung Cheng - San Jose CA

Assignee:

Marvell International, Ltd. - Hamilton

International Classification:

G11B 509

US Classification:

360 45, 360 51

Abstract:

In a precompensation circuit for magnetic recording of data signals, a clock produces clock signals at a predetermined rate to clock the recording of the data signals. A clock delay generator generates clock delay data relative to the generated clock signals for successive data signals to be recorded. The clock delay data for each data signal is formed according to the states of a set of adjacent data signals. n 1 programmable clock delay units operate sequentially to control the recording times of the successive data signals. Each clock delay unit receives the clock delay data for one data signal in each sequence of n successive data signals and determines recording time of the one data signal according to the clock delay data for the one data signal in the sequence.

Precompensation Circuit For Magnetic Recording

View page

US Patent:

6956708, Oct 18, 2005

Filed:

Mar 29, 2004

Appl. No.:

10/810893

Inventors:

Pantas Sutardja - San Jose CA, US
Chi Fung Cheng - San Jose CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G11B005/09

US Classification:

360 45, 360 51

Abstract:

In a precompensation circuit for magnetic recording of data signals, a clock produces clock signals at a predetermined rate to clock the recording of the data signals. A clock delay generator generates clock delay data relative to the generated clock signals for successive data signals to be recorded. The clock delay data for each data signal is formed according to the states of a set of adjacent data signals. n>1 programmable clock delay units operate sequentially to control the recording times of the successive data signals. Each clock delay unit receives the clock delay data for one data signal in each sequence of n successive data signals and determines recording time of the one data signal according to the clock delay data for the one data signal in the sequence.

High Bandwidth Phase Locked Loop (Pll)

View page

US Patent:

7116144, Oct 3, 2006

Filed:

Mar 16, 2004

Appl. No.:

10/802597

Inventors:

Chi Fung Cheng - San Jose CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03L 7/06

US Classification:

327156, 327160, 327115, 327116

Abstract:

A phase locked loop (PLL) is provided. In one implementation, the PLL includes a feedback loop having a frequency multiplier and an integer divider to generate a divided signal. The PLL includes a re-sampling circuit operable to re-sample one or more digital pulses of the divided signal using one or more phase signals if a multiplication factor of the frequency multiplier does not divide evenly into the integer divisor.

Asymmetric Compensation Circuit

View page

US Patent:

7161752, Jan 9, 2007

Filed:

Nov 5, 2003

Appl. No.:

10/701491

Inventors:

Chi Fung Cheng - San Jose CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G11B 5/09
G11B 5/02

US Classification:

360 46, 360 65, 360 67, 360 68

Abstract:

An apparatus, method, and system for providing asymmetric signal correction in a HDD system using magneto-resistive (MR) heads for reading information stored thereon. The MR head produces a signal that is asymmetric, and an asymmetric correction circuit corrects the asymmetric signal for further processing. The asymmetric correction circuitry comprises a differential amplifier having a variable gain for producing a current proportional to the asymmetric signal. The differential amplifier is coupled with two high speed switches for producing an output signal having only positive polarity. When the asymmetric correction output signal combines with the input signal, the resultant signal approximates the inverse distortion of the asymmetric input signal.

Precompensation Circuit For Magnetic Recording

View page

US Patent:

7184231, Feb 27, 2007

Filed:

Oct 17, 2005

Appl. No.:

11/250373

Inventors:

Pantas Sutardja - San Jose CA, US
Chi Fung Cheng - San Jose CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G11B 5/09

US Classification:

360 45

Abstract:

In a precompensation circuit for magnetic recording of data signals, a clock produces clock signals at a predetermined rate to clock the recording of the data signals. A clock delay generator generates clock delay data relative to the generated clock signals for successive data signals to be recorded. The clock delay data for each data signal is formed according to the states of a set of adjacent data signals. n>1 programmable clock delay units operate sequentially to control the recording times of the successive data signals. Each clock delay unit receives the clock delay data for one data signal in each sequence of n successive data signals and determines recording time of the one data signal according to the clock delay data for the one data signal in the sequence.

Asymmetric Compensation Circuit

View page

US Patent:

7242545, Jul 10, 2007

Filed:

Dec 28, 2006

Appl. No.:

11/617333

Inventors:

Chi Fung Cheng - San Jose CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G11B 5/09

US Classification:

360 46, 360 65, 360 67, 360 68

Abstract:

Dedicated Interface Architecture For A Hybrid Integrated Circuit

View page

US Patent:

7389487, Jun 17, 2008

Filed:

Apr 28, 1998

Appl. No.:

09/069054

Inventors:

King W. Chan - Los Altos CA, US
William C. T. Shu - Palo Alto CA, US
Sinan Kaptanoglu - Belmont CA, US
Chi Fung Cheng - San Jose CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 17, 716 16

Abstract:

An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.

Wikipedia References

Chi Cheng (Athlete)

Wikipedia

Shepard Fairey

View page

…On April 27, 2009, Fairey put three signed copies of his Obama inauguration posters up on eBay, with the proceeds of the auction going to the One Love For Chi foundation, founded by the family of Deftones bassist Chi Cheng following a car accident in November 2008 that nearly claimed Cheng's...

Chi Cheng (musician)

View page

Chi Cheng, (born July 15, 1970 in Davis, California) is a Chinese American musician, best known as the bass guitarist for the American band Deftones. ...