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Che Chao Hsu

from San Francisco, CA
Age ~46
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Also known as:
Che C Hsu, Checha Hsu, O Hsu
Phone and address:
470 Campbell Ave, San Francisco, CA 94134
Related to:
Andrew T Hsing, 38Shan D Hu, 77Fan Hsu, 74Tzong Hsu, 83Susan S Hsing, 66Jean-David Hsu, 42Steve H Chiao, 74Genevieve HsuYilei Hsu, 53Parents Hsu RayAi Hsu, 34Liwei W Kuo, 61Bonnie H Weng, 67Ray J Hsu, 38Jeandavid Y Hsu, 42Yueh Kuo SuMillie Hsu, 71Yu Y Hsu, 79Holly R Hsu, 85
Connected to:
Agnes Hsu, 50Alain Hsu, 70Allen Hsu, 37Amber B Hsu, 48Ami K Hsu, 57Anne Hsu, 36Anton N Hsu, 28Anya Hsu, 29Bailey Hsu, 46Bailing Hsu, 63

Che Hsu Phones & Addresses

  • 470 Campbell Ave, San Francisco, CA 94134
  • 1602 Butano Dr, Milpitas, CA 95035 (408) 942-9025
  • 2912 Creek Point Dr, San Jose, CA 95133 (408) 929-1820
  • Riverside, CA
  • Richmond, VA
  • Colton, CA
  • 1602 Butano Dr, Milpitas, CA 95035

Work

Position: Professional/Technical

Emails

j***[email protected]

Resumes

Resumes

Che Hsu Photo 1

Che Hsu

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Che Hsu Photo 2

Mitx On Edx

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Location:
670 east Gilbert St, San Bernardino, CA 92415
Industry:
Information Technology And Services
Work:
Oracle Jun 2012 - Jun 2017
Software Analyst at Oracle
San Francisco California Jun 2012 - Jun 2017
Mitx on Edx
Critical Logic Software Proto Tech Apr 2005 - Jun 2012
Senior Analyst
Flash Electronics Aug 2004 - Apr 2005
Process Engineer
Education:
University of California, Riverside 1997 - 2002
Bachelors, Bachelor of Science, Computer Science
Skills:
Management
Software Development
Oracle
Leadership
Management Consulting
Teaching
Strategic Planning
Corporate Social Responsibility
Social Entrepreneurship
Interests:
Education
Languages:
English
Mandarin
Che Hsu Photo 3

Co-Founder And Chief Technology Officer

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Location:
San Francisco, CA
Industry:
Internet
Work:
Snowflake Computing Oct 2014 - Aug 2015
Sales and Integration Engineer
Rakuten Jul 1, 2010 - Oct 2014
Principal Data Architect and Technician Lead and Scrum Master
Quotient Technology Inc. Apr 2008 - Jul 2010
Consumer Marketing Data Architect
Willington Research Apr 2008 - Jul 2010
Co-Founder and Chief Technology Officer
Loanperformance 2003 - 2004
Data Warehouse Architect For Prepayment Modeling
Education:
Landmark Education 2009 - 2009
Stanford University 2003 - 2006
California Polytechnic State University - San Luis Obispo 1991 - 1995
Bachelors, Bachelor of Science, Computer Engineering
Skills:
Manufacturing
Banking
Cloud Computing
Data Warehousing
Etl
Business Intelligence
Sql
Analytics
Agile Methodologies
Data Mining
Internet
Consumer Marketing
Bioinformatics
Clinical Data Management
Team Mentoring
Technical Hiring
Direct Sales
Sales Process
International Sales
Training
Scrum
Analysis
Scalability
Database Design
Hadoop
Oracle
Requirements Analysis
Big Data
Enterprise Software
Databases
E Commerce
Product Management
Strategy
Software Development
Linux
Saas
Consulting
Integration
Start Ups
Management
Software Project Management
Languages:
English
Mandarin

Business Records

Name / Title
Company / Classification
Phones & Addresses
Che Jie Hsu
President
WILLINGTON RESEARCH CORPORATION
Business Services at Non-Commercial Site
414 Stoneybrook Ct, Danville, CA 94506
404 Old Orch Ct, Danville, CA 94526
Che Hsu
Principal
Walden Research Group
Business Services
50 California St, San Francisco, CA 94111
Che Yuan Hsu
T.N.K. INCORPORATION
Che Yuan Hsu
EVERGREEN RESTAURANT INC
Che Jie Hsu
President
BRIAR CHASE ASSOCIATION - I
PO Box 503, Pleasanton, CA 94566
PO Box 2847, Danville, CA 94526
Che Hsiung Hsu
Managing
Daily Service
Consumer Services · Provide Transportation Services · Newspapers-Publishing/Printing
35975 Magellan Dr, Fremont, CA 94536

Publications

Us Patents

Angled Implantation For Deep Submicron Device Optimization

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US Patent:
7883946, Feb 8, 2011
Filed:
May 8, 2008
Appl. No.:
12/151646
Inventors:
Che Ta Hsu - San Jose CA, US
Christopher J. Pass - San Jose CA, US
Dale Ibbotson - Pleasanton CA, US
Jeffrey T. Watt - Palo Alto CA, US
Yanzhong Xu - Santa Clara CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H01L 21/84
H01L 21/22
H01L 21/38
US Classification:
438163, 438302, 438369, 438514, 438525, 438531, 257547, 257E21618, 257E21633
Abstract:
A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.

Integration Of Open Space/Dummy Metal At Cad For Physical Debug Of New Silicon

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US Patent:
8056025, Nov 8, 2011
Filed:
Feb 21, 2008
Appl. No.:
12/035403
Inventors:
Vijay Chowdhury - Fremont CA, US
Che Ta Hsu - San Jose CA, US
Ada Yu - San Francisco CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 17/50
G06F 19/00
G01R 31/28
US Classification:
716 54, 716111, 716136, 714 27, 714 30, 714733, 714734, 32475501, 324538
Abstract:
An access pad is used to provide access to a functional block of an integrated circuit (IC) device. The access pad is formed using dummy metal in an open space in a metallization level that is between a top metallization level and a base level on which the functional block is formed in the IC device. The access pad at the metallization level provides a contact to access an underlying circuit of the functional block so that the functional integrity of the functional block of the IC device can be verified during probing.

Photolithographic Reticles With Electrostatic Discharge Protection Structures

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US Patent:
8057964, Nov 15, 2011
Filed:
Oct 31, 2008
Appl. No.:
12/263413
Inventors:
Che Ta Hsu - San Jose CA, US
Peter J. McElheny - Morgan Hill CA, US
Jeffrey T. Watt - Palo Alto CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G03F 1/00
H01L 23/62
US Classification:
430 5, 257355
Abstract:
Photolithographic reticles are provided that have electrostatic discharge protection features. A photolithographic reticle may be formed from metal structures such as chrome structures on a transparent substrate such as fused silica. Some of the metal structures on the reticle correspond to transistors and other electronic devices on integrated circuits that are fabricated when using the reticles in a step-and-repeat lithography tool. These metal device structures may be susceptible to damage due to electrostatic charge build up during handling of the reticle. To prevent damage, dummy ring structures are formed in the vicinity of device structures. The dummy ring structures may be constructed to be more sensitive to electrostatic discharge than the device structures, so that in the event of an electrostatic discharge, damage is confined to portions of the reticle that are not critical.

Integration Of Open Space/Dummy Metal At Cad For Physical Debug Of New Silicon

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US Patent:
8312407, Nov 13, 2012
Filed:
Oct 18, 2011
Appl. No.:
13/276266
Inventors:
Vijay Chowdhury - Fremont CA, US
Che Ta Hsu - San Jose CA, US
Ada Yu - San Francisco CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 17/50
G06F 19/00
G06F 11/16
H03K 19/00
H01L 25/00
G01R 31/28
US Classification:
716122, 716123, 716129, 716139, 716136, 716 54, 700108, 326 41, 326 47, 326101, 714 30, 714733, 714734, 32475003
Abstract:
An access pad is used to provide access to a functional block of an integrated circuit (IC) device. The access pad is formed using dummy metal in an open space in a metallization level that is between a top metallization level and a base level on which the functional block is formed in the IC device. The access pad at the metallization level provides a contact to access an underlying circuit of the functional block so that the functional integrity of the functional block of the IC device can be verified during probing.

Angled Implantation For Deep Submicron Device Optimization

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US Patent:
8519403, Aug 27, 2013
Filed:
Feb 4, 2011
Appl. No.:
12/931584
Inventors:
Che Ta Hsu - San Jose CA, US
Christopher J. Pass - San Jose CA, US
Dale Ibbotson - Pleasanton CA, US
Jeffrey T. Watt - Palo Alto CA, US
Yanzhong Xu - Santa Clara CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H01L 27/108
H01L 29/00
H01L 31/036
H01L 31/112
US Classification:
257 69, 257E21633, 257E21618, 257E21547, 438949, 438948, 438952, 438950, 438163, 438302, 438369, 438512, 438525, 438531
Abstract:
A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.

Methods Of Forming Gate Structures For Reduced Leakage

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US Patent:
20130157451, Jun 20, 2013
Filed:
Dec 20, 2011
Appl. No.:
13/331055
Inventors:
Fangyun Richter - San Jose CA, US
Che Ta Hsu - San Jose CA, US
Wen Sun Wu - Bayan Lepas, MY
International Classification:
H01L 21/3205
G06F 17/50
US Classification:
438587, 716110, 257E21294
Abstract:
Integrated circuits containing transistors are provided. A transistor may include a gate structure formed over an associated well region. The well region may be actively biased and may serve as a body terminal. The well region of one transistor may be formed adjacent to a gate structure of a neighboring transistor. If the gate structure of the neighboring transistor and the well region of the one transistor are both actively biased and are placed close to one another, substantial leakage may be generated. Computer-aided design tools may be used to identify actively driven gate terminals and well regions and may be used to determine whether each gate-well pair is spaced sufficiently far from one another. If a gate-well pair is too close, the design tools may locate an existing gate cut layer and extend the existing gate cut layer to cut the actively driven gate structure.
Control profile
Che Chao Hsu from San Francisco, CA, age ~46 Get Report