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Charles D Stormon

from Cazenovia, NY
Age ~64

Charles Stormon Phones & Addresses

  • 1766 Us Route 20 W, Cazenovia, NY 13035 (315) 655-5868
  • 1766 Us Route 20 APT 20, Cazenovia, NY 13035
  • Westford, MA
  • Jamesville, NY
  • East Syracuse, NY
  • Syracuse, NY
  • 1766 Us Route 20, Cazenovia, NY 13035 (718) 787-5414

Work

Position: Machine Operators, Assemblers, and Inspectors Occupations

Education

Degree: High school graduate or higher

Business Records

Name / Title
Company / Classification
Phones & Addresses
Charles D. Stormon
Director
STELEUS INC
68 Tadmuck Rd, Westford, MA 01886
1 Technology Park Dr, Westford, MA 01886

Publications

Us Patents

Methods, Systems, And Computer Program Products For Providing Configurable Telecommunications Detail Record Adapter

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US Patent:
7286647, Oct 23, 2007
Filed:
Jan 18, 2005
Appl. No.:
11/037532
Inventors:
Charles D. Stormon - Cazenovia NY, US
Sanjay Ambardar - New Delhi, IN
Kuldeep Sharma - New Delhi, IN
Vijay Singh - Jhansi, IN
Assignee:
Tekelec - Morrisville NC
International Classification:
H04M 1/24
H04M 3/08
H04M 3/22
US Classification:
379 3201, 379 3203, 37911201, 379126
Abstract:
Methods, systems, and computer program products for providing a configurable telecommunications detail record adapter are disclosed. In one method, a user defines input data formats and output data formats via a graphical user interface. The text entered by the user is converted into a configuration file. The configuration file is converted into source code, and the source code is automatically converted into an executable adapter instance. In this manner, different adapter instances may be quickly and easily created by the user to process different input telecommunications detail record formats, such as formats of different probe vendors.

Instruction Set For A Content Addressable Memory Array With Read/Write Circuits And An Interface Register Logic Block

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US Patent:
58600850, Jan 12, 1999
Filed:
Aug 1, 1994
Appl. No.:
8/284372
Inventors:
Charles D. Stormon - Syracuse NY
Edward Saleh - Syracuse NY
Nikos B. Troullinos - Syracuse NY
Raymond M. Leong - Los Altos CA
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G06F 1200
US Classification:
711108
Abstract:
An associative processing memory system for concurrent data searching and concurrent data processing which includes content addressable memory (CAM) array having multiple CAM words; a multiplexer for executing one of the input devices and for passing an output of one of the input devices; an interface register logic block for storing instructions in a command register and control and status information in a control and status register; a match circuit for executing a match instruction for performing a masked comparison of data in every CAM word in the CAM array to a search pattern; a read circuit for executing a read instruction for reading one CAM word in the CAM array wherein the CAM word is selected using a response register A and a multiple response resolver (MRR); a write circuit for executing a write instruction for performing a masked write operation to every CAM word indicated by a bit set in a select vector; a shift circuit for executing a shift instruction for shifting the response register A up or down by one bit position; a clear circuit for executing an instruction for clearing the most significant bit set in the response register A; a move circuit for executing a move instruction for writing the data contents indicated by the select vector to a response register; a write-column circuit for executing an instruction for writing the contents of the select vector to a column in the CAM array; a circuit for executing an nop instruction for performing no operation; a read-shift for executing a readshift instruction; a read-snext circuit for executing a readsnext instruction; a write-shift circuit for executing a writeshift instruction; and a write-snext circuit for executing a writesnext instruction.

Integrated Content Addressable Memory Array With Processing Logical And A Host Computer Interface

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US Patent:
56491492, Jul 15, 1997
Filed:
Aug 1, 1994
Appl. No.:
8/284347
Inventors:
Charles D. Stormon - Syracuse NY
Abhijeet Chavan - Ann Arbor MI
Nikos B. Troullinos - Syracuse NY
Raymond M. Leong - Los Altos CA
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G06F 1202
G06F 1300
US Classification:
395435
Abstract:
An associative processing memory system for concurrent data searching or processing includes a content addressable memory (CAM) array, a general register block, an interface register logic block, and a general control block. The CAM array is accessed for read or write by a select vector generated by the general register logic block. The select vector is selected through a multiplexer from at least four sources: the match latch, the multiple response resolver, the general purpose logic block and a supplies one unit. The interface register logic block provides input/output data registers, mask register, command register, and control/status register. The general control block generates control signals to the CAM system in response to bus signals. The match operation for the CAM array can be performed on all words in a single operation. A set of CAM instructions is used to control CAM operations including data movement, shifting, read/write, and match.
Charles D Stormon from Cazenovia, NY, age ~64 Get Report