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Charles L Sobchak

from Sea Ranch Lakes, FL
Age ~52
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Also known as:
Charles Sobachak, Charles K
Phone and address:
32 Cayuga Rd, Fort Lauderdale, FL 33308
Related to:
Edward SobchakJohn J Bellini, 55Patricia J Bellini, 78Alicia B Sobchak, 52Alyce D Sobchak, 89John J Bellini, 81Wendy K Magee, 50Frank K Sobchak, 97
Connected to:
Susie W Sobchak, 64Bartosz D Sobczak, 43Carolyn J Sobczak, 75Chris J Sobczak, 56Cody Sobczak, 31Dawn M Sobczak, 74Fulya Sobczak, 65Jesse Sobczak, 34Joanne Sobczak, 69Kathryn L Sobczak, 69

Charles Sobchak Phones & Addresses

  • 32 Cayuga Rd, Ft Lauderdale, FL 33308
  • 87 Isle Of Venice Dr, Ft Lauderdale, FL 33301 (954) 462-7268
  • Sea Ranch Lakes, FL
  • Davie, FL
  • New Smyrna Beach, FL
  • 720 34Th St, Gainesville, FL 32607 (352) 335-9212
  • 540 Greaton Ave, Davie, FL 33325

Work

Company: Concurrent real-time Jun 2017 Position: Fpga ip r and d engineer

Education

Degree: Master of Science, Masters School / High School: University of Florida 1997 to 1998 Specialities: Electrical Engineering

Skills

Digital Signal Processors • Embedded Systems • Signal Processing • Semiconductors • Embedded Software • Rf • Ic • Simulations • Product Management • Software Development • Hardware Architecture • Wireless • Lte • Debugging • Mobile Devices • Unix • Electronics • Matlab • Integrated Circuit Design • Algorithms • System Architecture • Testing • Firmware • Cellular Communications • Telecommunications • C • Systems Engineering • Electrical Engineering • Fpga • Software Engineering • Cdma • Wimax • Asic • Linux • C++ • Architectures

Industries

Telecommunications

Resumes

Resumes

Charles Sobchak Photo 1

Fpga Ip R And D Engineer

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Location:
Fort Lauderdale, FL
Industry:
Telecommunications
Work:
Concurrent Real-Time
Fpga Ip R and D Engineer
Motorola Solutions Sep 2014 - Jun 2017
Project Lead and Systems and Signal Processing
Motorola Solutions Jul 2010 - Sep 2014
Signal Processing Research
Fujitsu Apr 2009 - Jul 2010
Systems and Architecture Engineer
Freescale Semiconductor 2005 - 2009
Systems and Architecture Engineer
Education:
University of Florida 1997 - 1998
Master of Science, Masters, Electrical Engineering University of Florida 1990 - 1995
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Digital Signal Processors
Embedded Systems
Signal Processing
Semiconductors
Embedded Software
Rf
Ic
Simulations
Product Management
Software Development
Hardware Architecture
Wireless
Lte
Debugging
Mobile Devices
Unix
Electronics
Matlab
Integrated Circuit Design
Algorithms
System Architecture
Testing
Firmware
Cellular Communications
Telecommunications
C
Systems Engineering
Electrical Engineering
Fpga
Software Engineering
Cdma
Wimax
Asic
Linux
C++
Architectures

Business Records

Name / Title
Company / Classification
Phones & Addresses
Charles Lmgrm Sobchak
Managing
SOBCHAK VENTURES, LLC
32 Cayuga Rd, Fort Lauderdale, FL 33308
540 Greaton Ave, Fort Lauderdale, FL 33325
Charles Sobchak
ALICIA BELLINI DESIGN, INC
32 Cayuga Rd, Fort Lauderdale, FL 33308
Charles L. Sobchak
Chief Financial Officer
BLUE2 Design Inc
Graphic Design Company
540 Greaton Ave, Fort Lauderdale, FL 33325

Publications

Us Patents

Method And Apparatus For Shared Processing A Plurality Of Signals

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US Patent:
7142606, Nov 28, 2006
Filed:
Sep 27, 2002
Appl. No.:
10/256906
Inventors:
Sumit Anil Talwalkar - Plantation FL, US
Charles Leroy Sobchak - Davie FL, US
Mahibur Rahman - Lake Worth FL, US
Assignee:
FreeScale Semiconductor, Inc. - Austin TX
International Classification:
H04L 27/00
H03M 1/00
G06F 17/10
H03F 1/02
US Classification:
375259, 341143, 208317, 330 9
Abstract:
A signal processing apparatus preferably suitable for implementation as an integrated circuit, that is arranged and constructed to be shared for processing a plurality of signals without interference between the signals and method thereof, the signal processing apparatus comprising: an input multiplexer for sequentially selecting from among the plurality of signals to provide a sequence of selected signals; a processing unit for processing the sequence of selected signals to provide a sequence of processed signals, the processing unit having an input coupled to the input multiplexer and a delay stage including a plurality of series coupled delay elements with one delay element corresponding to each of the plurality of signals; and an output de-multiplexer for sequentially selecting from the sequence of processed signals to provide a plurality of processed signals corresponding one to one with the plurality of signals.

Low Cost And High Performance Narrowband Interference Cancellation System

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US Patent:
7324616, Jan 29, 2008
Filed:
Mar 1, 2004
Appl. No.:
10/790168
Inventors:
Charles L. Sobchak - Davie FL, US
Mahibur Rahman - Lake Worth FL, US
David R. Haub - San Diego CA, US
Louis J. Vannatta - Crystal Lake IL, US
Assignee:
Motorola, Inc. - Libertyville IL
International Classification:
H03D 1/04
US Classification:
375346, 375144, 375229, 375316, 375350, 455 6711, 455 631, 455522
Abstract:
A narrowband interference cancellation system, method and digital signal processor is disclosed that removes narrowband interference in wide band communication systems. The system includes a narrowband processing component, wideband processing component, soft metric generator and at least one filter. The system is configured to receive a signal, identify one or more narrowband interferers in the received signal and filter out identified narrowband interferers. The narrowband processing component includes a filter bank configured to separate the received signal into a predetermined number of channel bands and identify a band with interference. The wide band processing component provides an average level for an unfiltered version of the received signal. The soft decision metric generator produces metrics based on predetermined thresholds. The filters receive coefficients that are determined using outputs from the soft decision metric generator that are first averaged using long term integrators and then stored in lookup tables.

Method And Apparatus For Compensating For Variations In A Receive Portion Of A Wireless Communication Device

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US Patent:
7385913, Jun 10, 2008
Filed:
Apr 24, 2002
Appl. No.:
10/131660
Inventors:
Charles Leroy Sobchak - Davie FL, US
Mahibur Rahman - Lake Worth FL, US
Clinton C Powell - Austin TX, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H04J 11/00
H04B 7/216
US Classification:
370203, 370335, 370342
Abstract:
A generator () generates first and second training signals () that originate within a wireless communication device (FIG. ) instead of being received from a source outside the device. A receive portion () of the device processes the first training signal to derive a processed training signal. An adaptive equalizer () equalizes the processed training signal to derive an equalized training signal. A processor () compares the equalized training signal and the second training signal using an adaptive algorithm to derive coefficients for the adaptive equalizer to compensate for variations in the receive portion, and adjusts the adaptive equalizer in accordance with the coefficients to derive a compensated output signal.

Method And Apparatus For Dynamic Gain And Phase Compensations

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US Patent:
7486941, Feb 3, 2009
Filed:
Apr 4, 2005
Appl. No.:
11/099278
Inventors:
Mahibur Rahman - Lake Worth FL, US
Charles L. Sobchak - Davie FL, US
James David Hughes - Boynton Beach FL, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H04B 1/26
US Classification:
4552341, 4552501
Abstract:
Dynamic gain and phase compensation is provided in a radio frequency (RF) receiver () including at least one switched Low Noise Amplifier (LNA) () coupled to an RF gain control unit () providing a gain control signal to the at least one switched LNA () for control thereof. The RF receiver also includes an analog-to-digital (A/D) converter () for digitizing the RF signal and outputting an N-bit digital signal to the RF gain control unit (). The method for gain compensation includes dynamically adjusting the N-bit digital signal to compensate for the at least one switched LNA () in response to the gain control signal. The method for phase compensation includes dynamically normalizing the N-bit digital signal into an M-bit signal range to derive an M-bit digital signal, where M≦N and dynamically phase adjusting the M-bit digital signal to compensate for the at least one switched LNA () in response to the gain control signal.

Dc Offset Correction For Direct Conversion Receivers

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US Patent:
7603094, Oct 13, 2009
Filed:
Jun 14, 2006
Appl. No.:
11/452457
Inventors:
Mahibur Rahman - Lake Worth FL, US
Charles L. Sobchak - Davie FL, US
Assignee:
Freescale Semiconductor Inc. - Austin TX
International Classification:
H04B 7/00
H04Q 7/20
US Classification:
4552411, 4552532, 455296, 455324
Abstract:
A direct current (DC) offset correction system for a direct conversion receiver and corresponding receiver and methods facilitate reduction of DC offsets in such receivers. One method includes calibrating a DC offset correction system in a closed loop configuration over each of a plurality of gain settings to provide a plurality of offset data for an operating mode of the direct conversion receiver; selecting one of the plurality of offset data based on a current gain setting of the direct conversion receiver as supplied, e. g. , by an AGC system; and operating the DC offset correction system in an open loop configuration using the one of the plurality of offset data to correct for a DC offset in the direct conversion receiver.

Dc Offset Correction For Constant Envelope Signals

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US Patent:
7693242, Apr 6, 2010
Filed:
Jun 14, 2005
Appl. No.:
11/151752
Inventors:
Charles L. Sobchak - Davie FL, US
Mahibur Rahman - Lake Worth FL, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H04B 1/10
US Classification:
375349, 375225, 375219, 375332, 375130, 375343, 327307, 327306, 455 631, 455312
Abstract:
Methods () and corresponding systems () for determining and correcting a DC offset in a receiver operate to sample () a signal to provide complex samples; estimate () a Direct Current (DC) offset corresponding to each of the complex samples, the estimating the DC offset further including solving a plurality of equations relating to the plurality of complex samples, e. g. , N simultaneous equations in N samples with a power of the signal invariant across the N samples, to deterministically derive offset values; and then remove () the DC offset from the signal.

Automatic Gain Control Using Multiple Equalized Estimates Dynamic Hysteresis

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US Patent:
7760816, Jul 20, 2010
Filed:
Jan 11, 2007
Appl. No.:
11/622402
Inventors:
Charles LeRoy Sobchak - Davie FL, US
Mahibur Rahman - Lake Worth FL, US
Lynn R. Freytag - Deerfield Beach FL, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H04K 1/02
H04L 27/06
H04B 1/06
H04B 7/00
US Classification:
375297, 375345, 330278, 330295, 4552341, 4552532
Abstract:
At least one adjustable gain analog amplifier ( and ) in an analog line-up () amplifies by a gain an analog signal at an input of the analog line-up (). The at least one adjustable gain analog amplifier ( and ) is operable at one or more gains. At least one digital estimation device ( and ) receives signal via an output () of the analog line-up () and provides a digital signal estimate representative of an analog signal at an input of a respective one of the at least one adjustable gain analog amplifier ( and ) in the analog line-up (). An AGC controller () monitors the digital signal estimate. The AGC controller () adjusts the gain of the at least one analog amplifier ( and ). An RF receiver and an integrated circuit utilizing the novel features are also disclosed.

Fractionally Related Multirate Signal Processor And Method

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US Patent:
7782991, Aug 24, 2010
Filed:
Jan 9, 2007
Appl. No.:
11/621387
Inventors:
Charles LeRoy Sobchak - Davie FL, US
Mahibur Rahman - Lake Worth FL, US
Emilio J. Quiroga - Lake Worth FL, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H04L 7/00
H03D 3/24
US Classification:
375355, 375373
Abstract:
A multirate processing circuit () with a resampling filter () to accept a sampled input signal () sampled with a first clock rate and to filter the sampled input signal to remove spectral components above a spectral bandwidth of a second clock rate. The sampled input signal represents a signal that is more efficiently processed at the second clock rate, which is fractionally related to the first clock rate. The multirate processing circuit () also has a discrete time processor () that receives the resampling filter output () and processes that output at an integer power of two multiple of the first clock rate. The discrete time processor () further excludes selected samples from the processing so as to effectively perform discrete time processing of the resampling filter output () at the integer power of two multiple of the second clock rate.
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Charles L Sobchak from Sea Ranch Lakes, FL, age ~52 Get Report