Charles K Erdelyi

7197446, Mar 27, 2007

Aug 30, 2004

10/711168

Erik Breiland - Colchester VT, US
Timothy W. Budell - Milton VT, US
Charles S. Chiu - Essex Junction VT, US
Paul L. Clouser - Williston VT, US
Charles K. Erdelyi - Essex Junction VT, US
Brian P. Welch - Scotia NY, US

International Business Machines Corporation - Armonk NY

G06F 17/50

703 14, 703 2, 716 1, 716 4, 716 10

The invention relates generally to a method of power supply noise and signal integrity analysis for creating frequency-dependent electrical models particularly related to microelectronic packages. The method discloses creation of equivalent circuits for geometries encountered in a typical chip package, including how to partition the geometry into cells which are less then 1/20 the minimum wavelength (λ) in size, and how to handle signal and power supply vias, signal wires, and power planes. The method also instructs how to assign values to each of the inductors, capacitors, resistors, and transmission lines in each equivalent circuit. The method further provides modeling of only those interactions which occur between adjacent cells.

44463839, May 1, 1984

Oct 29, 1982

6/437609

Michael P. Concannon - Jericho VT
Charles K. Erdelyi - Essex VT

International Business Machines - Armonk NY

G05F 316

307297

A reference voltage generating circuit comprising a depletion mode FET transistor connected to provide a constant current source coupled between a supply voltage and an output node. Three serially connected enhancement mode FET transistors are connected between the output node and a reference voltage. The first enhancement mode device is diode coupled to provide an enhancement threshold voltage offset, the second enhancement mode device has its gate electrode connected to the supply voltage to compensate for variations in supply voltage and the third enhancement device has its gate electrode connected to a source follower circuit. The source follower circuit comprises two serially connected depletion mode devices which receive an input from the output node and provide a feedback output to the gate electrode of the third enhancement mode device so that a constant voltage of a predetermined magnitude is maintained at the output node.

49808893, Dec 25, 1990

Dec 29, 1988

7/291727

Wayne J. DeGuise - Colchester VT
Charles K. Erdelyi - Essex Junction VT
Steven F. Oakland - Colchester VT

G06F 1100

371 223

A multi-mode testing system is provided which includes first, second and third selector circuits, each of which has a control circuit for selecting one of first and second paths connected to an output, and a single shift register latch having first and second input ports and an output. The first path of the first selector circuit and of the second selector circuit is connected to a data output terminal of a logic circuit under test and the output of the third selector circuit is connected to a data input terminal of the logic circuit under test. A driver circuit has an input connected to the output of the first selector circuit and an output connected to an input/output terminal, with the input/output terminal also being coupled to the first path of the third selector circuit and to the second path of the second selector circuit. The first input port of the latch is connected to the output of the second selector circuit, the second input port is coupled to a scan data input terminal and the output of the latch is connected to the second path of the first selector circuit and of the third selector circuit.

61182613, Sep 12, 2000

Nov 8, 1993

8/148452

Charles Karoly Erdelyi - Essex Junction VT
John Edwin Gersbach - Burlington VT

International Business Machines Corp. - Armonk NY

G05F 316
H02M 318

323313

A noise limited, video, digital to analog converter having an output transition time control with multiple discrete transition times. This is accomplished by a DAC control circuit in which the slew rate of the current is controlled by providing set current levels in the inverters that drive the DAC output current switches thus limiting the current available for charging and discharging the capacitance on the nodes which control the output signal. Additional control is provided by voltage clamping of these nodes which reduces the input voltage to the analog output and results in a cleaner output waveform. By so regulating and controlling the charging and discharging of these nodes, the variations in operation of the circuit due to the process used to produce the circuit in integrated form as well as temperature and supply voltage are further substantially reduced.

49528181, Aug 28, 1990

May 17, 1989

7/353378

Charles K. Erdelyi - Essex Junction VT
Timothy P. Reed - Cary NC

International Business Machines Corporation - Armonk NY

H03K 1716
H03K 19017
H03K 1921

307270

A driver circuit is provided which includes an output stage having first and second transistors and an output terminal, the first transistor being of a first type conductivity is coupled from the output terminal to a first point of reference potential and the second transistor being of a second type conductivity is coupled from the output terminal to a second point of reference potential. A first voltage divider includes transistors of the first type conductivity and a second voltage divider includes transistors of the second type conductivity. A second transistor of the first type conductivity is connected between the first point of reference potential and a control electrode of the first transistor of the first type conductivity and a second transistor of the second type conductivity is connected between the second point of reference potential and a control electrode of the first transistor of the second type conductivity. An input terminal and the output terminal are connected to the first and second voltage dividers, with an output from the first divider being connected to the control electrode of the first transistor of the second type conductivity and with an output of the second divider being connected to the control electrode of the first transistor of the first type conductivity. Transistors of the first and second type conductivities are preferably P-channel and N-channel field effect transistors, respectively.

50598376, Oct 22, 1991

Feb 13, 1989

7/309530

Charles K. Erdelyi - Essex Junction VT
Mark G. Marshall - Essex Junction VT

IBM - Armonk NY

H03K 513
H03K 5159
H03K 1728

307601

A delay circuit for receiving a number of input signals and for providing a delay in accordance with the input signals. The delay circuit includes: an output circuit for producing a first output signal when a node is above a threshold voltage, and for producing a second output signal, which is different from the first output signal, when the node is below the threshold voltage; a device for maintaining the node voltage at a level which is above the threshold voltage so that the output circuit produces the first output signal; and a plurality of switching devices for causing, the node voltage to decrease below the threshold voltage so that the output circuit produces the second output signal. Depending on which one of the switching devices is rendered conductive, the node voltage will decrease at a different rate, thereby causing the output circuit to produce the second output signal at different delay times.

51824680, Jan 26, 1993

May 6, 1991

7/696380

Charles K. Erdelyi - Essex Junction VT
Mark G. Marshall - Essex Junction VT
John W. Mathews - Burlington VT
Patrick E. Perry - Colchester VT

IBM Corporation - Armonk NY

G05F 316
G05F 320

3072961

A current limiting clamp circuit for providing a clamped voltage at a node and including a P-type MOS transistor and several N-type MOS transistors which are connected in series between the drain of the P-type MOS transistor and ground, with one of the N-type transistors having its gate and drain connected to the drain of the P-type transistor, and having its source connected to the node. In another embodiment, the current limiting clamp circuit includes a pair of P-type transistors and several N-type transistors, with one of the P-type transistors having its source connected to a power supply, its gate connected to ground and its drain connected to the source of the other P-type transistor which has its gate and drain connected to the node.

47790156, Oct 18, 1988

May 26, 1987

7/053670

Charles K. Erdelyi - Essex Junction VT

International Business Machines Corporation - Armonk NY

H03K 19092
H03K 1716
H03K 19017

307475

A simple CMOS receiver or buffer circuit is provided which includes a first inverter having its output connected to the input of a second inverter with rapid switching action in the first inverter at even low input voltage swings achieved by a parallel circuit that alters the first inverter switching point under the control of the applied input voltage. Third and fourth inverters are added for increasing the drive capability of the circuit.