Chandra M Guda

20130132638, May 23, 2013

Nov 21, 2011

13/301543

Robert L. Horn - Yorba Linda CA, US
Jing Booth - San Jose CA, US
Chandra M. Guda - Lake Forest CA, US

WESTERN DIGITAL TECHNOLOGIES, INC. - Irvine CA

G06F 12/00

711103, 711E12008

A disk drive is disclosed that utilizes multi-tiered solid state memory for caching data received from a host. Data can be stored in a memory tier that can provide the required performance at a low cost. For example, multi-level cell (MLC) memory can be used to store data that is frequently read but infrequently written. As another example, single-level cell (SLC) memory can be used to store data that is frequently written. Improved performance, reduced costs, and improved power consumption can thereby be attained.

20120284460, Nov 8, 2012

May 2, 2011

13/099316

CHANDRA M. GUDA - LAKE FOREST CA, US

WESTERN DIGITAL TECHNOLOGIES, INC. - Irvine CA

G06F 12/00

711114, 711E12001

Embodiments of solid-state storage system are provided herein which reduce processing delays for performance-sensitive commands. These performance-sensitive commands are typically read-write commands which can be transferred to the storage media by a high performance path to optimize responsiveness to the host. This high performance path can be enabled and disabled to prevent conflicts with commands processed via a low performance path.

20220308958, Sep 29, 2022

Mar 24, 2021

17/211601

- Boise ID, US
Xiaoxin Zou - Singapore, SG
Chandra Mouli Guda - Fremont CA, US

G06F 11/10
G06F 11/07
G06F 11/30
G06F 12/02
G06F 12/0804
G06F 12/0891

A memory device includes a plurality of memory die blocks and a plurality of memory channels operably coupled to the plurality of memory die blocks and a memory controller configured to identify one or more memory die blocks as being invalid. The memory controller obtains a first matrix storing a mapping of memory channels to memory die blocks and creates a new mapping of memory channels to memory die blocks excluding the invalid memory die blocks. The new mapping is stored in a second matrix and one or more operations are performed on the memory die blocks based on the new mapping.

20220197535, Jun 23, 2022

Dec 17, 2020

17/125872

- Boise ID, US
Chandra Mouli Guda - Fremont CA, US

G06F 3/06

A memory device includes a plurality of groups of memory blocks, each group including a plurality of blocks, and each block including a plurality of memory units. A memory controller for the memory device performs operations including maintaining a count of valid memory units in the group for each group and maintaining a count of valid memory units in each block of the memory device. The operations further include selecting a first group based on a count of valid memory units and the first group including a target plurality of blocks. The operations further include selecting a first target block from the target plurality of blocks, determining whether the first target block is to be erased, and erasing the first target block in response to determining that the first target block is to be erased.

20220197563, Jun 23, 2022

Aug 20, 2021

17/407396

- Boise ID, US
Alex J. Wesenberg - Erie CO, US
Guanying Wu - Longmont CO, US
Sanjay Subbarao - Irvine CA, US
Chandra Guda - Fremont CA, US

G06F 3/06

The memory sub-systems of the present disclosure discloses a simulator to simulate a QoS latency model for a just-in-time (JIT) scheduler. In one embodiment, a system receives a workload profile specifying a sequence of memory operations, wherein each memory operation is associated with a type of the memory operation. The system identifies a traffic class associated with each memory operation of the sequence of memory operations. The system queues each memory operation of the sequence of memory operations, based on the traffic class associated with the memory operation, in a scheduling pool of a number of scheduling pools. The system selects, based on a quality of service (QoS) policy, from the scheduling pools, one or more memory operations to be serviced within a scheduling time frame. The system determines, based on a latency profile, latency periods for each memory operation of the one or more memory operations.

20220197837, Jun 23, 2022

Aug 20, 2021

17/407411

- Boise ID, US
Alex J. Wesenberg - Erie CO, US
Guanying Wu - Longmont CO, US
Sanjay Subbarao - Irvine CA, US
Chandra Guda - Fremont CA, US

G06F 13/16
G06F 13/37
G06F 9/50

The memory sub-systems of the present disclosure discloses a just-in-time (JIT) scheduling system and method. In one embodiment, a system receives a request to perform a memory operation using a hardware resource associated with a memory device. The system identifies a traffic class corresponding to the memory operation. The system determines a number of available quality of service (QoS) credits for the traffic class during a current scheduling time frame. The system determines a number of QoS credits associated with a type of the memory operation. Responsive to determining the number of QoS credits associated with the type of the memory operation is less than the number of available QoS credits, the system submits the memory operation to be processed at a memory device.

20220188240, Jun 16, 2022

Mar 8, 2022

17/689857

- Boise ID, US
Chandra Guda - Fremont CA, US
Steven Gaskill - Campbell CA, US

G06F 12/0893
G06F 13/16

A processing device in a memory system determines to send system state information associated with the memory device to a host system and identifies a subset of a plurality of event entries from a staging buffer based on one or more filtering factors, the plurality of event entries corresponding to events associated with the memory device. The processing device further sends the subset of the plurality of event entries as the system state information to the host system over a communication pipe having limited bandwidth.

20230008307, Jan 12, 2023

Jul 7, 2021

17/369073

- Boise ID, US
Chandra M. Guda - Fremont CA, US

G06F 3/06

Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command specifying a logical address; determining a physical address associated with the logical address; determining a portion of the memory device that is referenced by the physical address; determine an endurance factor associated with the portion; and increasing, by a value derived from the endurance factor, a media management metric associated with a management unit of the memory device, wherein the management unit is referenced by the physical address.