Carroll C Speir

7719452, May 18, 2010

Sep 23, 2008

12/284672

Scott Gregory Bardsley - Gibsonville NC, US
Bryan Scott Puckett - Stokesdale NC, US
Michael Ray Elliott - Summerfield NC, US
Ravi Kishore Kummaraguntla - Austin TX, US
Ahmed Mohamed Abdelatty Ali - Oak Ridge NC, US
Carroll Clifton Speir - Pleasant Garden NC, US
James Carroll Camp - Greensboro NC, US

Analog Devices, Inc. - Norwood MA

H03M 1/20

341131, 341118, 341120, 341155, 341161, 341162

Signal converter system embodiments are provided to substantially reduce symmetrical and asymmetrical conversion errors. Signal-processing stages of these embodiments may include a signal sampler in addition to successively-arranged signal converters. In system embodiments, injected analog dither signals are initiated in response to a random digital code. They combine with a system's analog input signal and the combined signal is processed down randomly-selected signal-processing paths of the converter system to thereby realize significant improvements in system linearity. Because these linearity improvements are realized by simultaneous processing of the input signal and the injected dither signal, a combined digital code is realized at the system's output. A first portion of this combined digital code corresponds to the analog input signal and a second portion corresponds to the injected analog dither signal. The final system digital code is realized by subtracting out the second portion with a back-end decoder that responds to the random digital code.

20070290913, Dec 20, 2007

Apr 2, 2007

11/731926

William George John Schofield - North Andover MA, US
Joseph Bradford Bannon - Greensboro NC, US
Carroll Speir - Pleasant Garden NC, US
Scott Bardsley - Summerfield NC, US

H03M 1/12

341155

An analog to digital converter system includes at least one stage for providing a first full precision, full latency output and a second output providing a less than full latency, less than full precision coarse level indicator signal.

20120114077, May 10, 2012

Nov 8, 2010

12/941361

Joseph Bradford BRANNON - Greensboro NC, US
David Hall Robertson - Boxford MA, US
James C. Camp - Greensboro NC, US
Carroll C. Speir - Pleasant Garden NC, US

Analog Devices, Inc. - Norwood MA

H04L 27/00
H03M 7/30

375316, 341 87

Embodiments of the present invention may provide a signal processing circuit that may comprises an analog-to-digital converter (ADC), and an output restriction circuit. The output restriction circuit may reduce the accuracy of the digital output of the ADC when signal content exceeds a pre-determined spectrum mask in an undesirable band. In one embodiment, the input signal spectrum may be actively monitored and when the input spectrum is inconsistent with an intended application, the output resolution may be restricted, for example, by truncating least significant bits (LSBs) of the digital output or adding digital noise.

20190341922, Nov 7, 2019

May 21, 2019

16/418777

- Norwood MA, US
Kenny Gentile - Burlington NC, US
Carroll C. Speir - Pleasant Garden NC, US
Matthew D. McShea - Summerfield NC, US
Matthew Louis Courcy - Fremont NH, US
Reuben Pascal Nelson - Colfax NC, US

H03L 7/087
H03L 7/06
H03K 5/15
H03L 7/081
H04L 7/02

Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.

20190190530, Jun 20, 2019

Dec 18, 2017

15/845796

- Norwood MA, US
Carroll C. SPEIR - Pleasant Garden NC, US
Eric OTTE - Boston MA, US
Corey PETERSEN - Poway CA, US
Jeffrey P. BRAY - San Diego CA, US

Analog Devices, Inc. - Norwood MA

H03M 1/10

To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.

20180115406, Apr 26, 2018

Oct 24, 2016

15/332152

- NORWOOD MA, US
RYAN LEE BUNCH - GREENSBORO NC, US
CARROLL C. SPEIR - PLEASANT GARDEN NC, US

ANALOG DEVICES, INC. - NORWOOD MA

H04L 7/00

A time-to-digital converter (TDC) detects a timing relationship between signals representing two temporal events. Several samples are acquired over a certain time period for each event, and the signals related to the different events are digitized or quantized either by separate TDCs or by a single TDC in a time-sequential manner. The quantized results are then processed, for example added to/ subtracted from one another, and used to determine the phase or time difference between the two events. When information being quantized is quasi-static over time periods where the measurement is performed, the instantaneous or “one shot” accuracy of a TDC need not be as good as or better than the desired time resolution. Digitally processing the signals and averaging the results moves an otherwise difficult analog quantizer problem to the digital domain where savings in power and chip area can be easily achieved without sacrificing accuracy.

20180102779, Apr 12, 2018

Oct 6, 2016

15/287435

- Norwood MA, US
Reuben Pascal Nelson - Colfax NC, US
Matthew D. McShea - Summerfield NC, US
Matthew Louis Courcy - Fremont NH, US
Kenny Gentile - Burlington NC, US
Carroll C. Speir - Pleasant Garden NC, US

H03L 7/087
H03K 5/15
H03L 7/081
H04L 7/02

Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.

20160182075, Jun 23, 2016

Dec 1, 2015

14/955905

- NORWOOD MA, US
ERIC OTTE - BOSTON MA, US
NEVENA RAKULJIC - SAN DIEGO CA, US
CARROLL C. SPEIR - PLEASANT GARDEN NC, US

ANALOG DEVICES, INC. - NORWOOD MA

H03M 1/10
H03M 1/46
H03M 1/12

Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.