Carlo J Evangelisti

42863210, Aug 25, 1981

Jun 18, 1979

6/049532

David C. Baker - Austin TX
David F. Bantz - Chappaqua NY
Carlo J. Evangelisti - Jefferson Valley NY

International Business Machines Corporation - Armonk NY

G06F 704

364200

The technique for transmitting address information between a processor and a plurality of memory subsystems in a common bus communication system. The width of the address field is greater than the number of lines on the bus. For example, addresses are three bytes wide, and the bus is one byte wide, thereby reducing the number of pins required on the processor and the subsystems. For communication between the processor and a given memory subsystem, only those bytes of a selected address which differ from the corresponding bytes of a previous address are transmitted sequentially for accessing a selected memory location.

48232815, Apr 18, 1989

Dec 4, 1987

7/129970

Carlo J. Evangelisti - Jefferson Valley NY
Leon Lumelsky - Stamford CT

IBM Corporation - Armonk NY

G06F 314

364518

A color graphic processor includes one or more processing elements responsive to pixel data provided by a frame buffer. The processing element stores pixels from the frame buffer in source and destination registers. The arithmetic logic unit (ALU) portion of the processing element includes a random access memory (RAM) addressed by the registers to produce a result pixel value which can be written back to the frame buffer. The RAM can implement a wide variety of pixel operations by loading the RAM with operation specific data.

43120660, Jan 19, 1982

Dec 28, 1979

6/107992

David F. Bantz - Chappaqua NY
Carlo J. Evangelisti - Jefferson Valley NY
Robert A. Nelson - Katonah NY

International Business Machines Corporation - Armonk NY

G06F 1122

371 16

A system is described for enabling the connection of a diagnostic/debugging processor to another host processor for the purpose of troubleshooting that processor's hardware and software. The system is composed of an interface between the diagnostic/debugging processor per se and the host processor to be diagnosed, and of software resident in the diagnostic processor to perform functions required by the user of the system. The system is specifically designed for use with a host processor utilizing LSSD design rules.

47316063, Mar 15, 1988

Aug 2, 1985

6/762348

David F. Bantz - Chappaqua NY
Carlo J. Evangelisti - Jefferson Valley NY

International Business Machines Corporation - Armonk NY

G09G 116

340709

A method for rapid windowing of display information in computer graphics is disclosed herein. Image display data is maintained in a hierarchical data tree structure. Small numbers of bits of data called summaries are maintained at the nodes of the tree. The large complete data image is divided into units called boxes. These boxes combine to form a master box for a particular window size. By searching the summaries for each box and locating the window within the master box, traversal of an entire subtree may be terminated quickly, proceed on only some of the subtrees, or proceed through to completion. A clipped image is rapidly generated that can be rendered to the viewer.

53923855, Feb 21, 1995

May 22, 1992

7/888385

Carlo J. Evangelisti - Jefferson Valley NY
Leon Lumelsky - Stamford CT
Mark J. Pavicic - Fargo ND

International Business Machines Corporation - Armonk NY

G06F 1562

395131

SIMD computer architecture is used in conjunction with a host processor and coordinate processor to render quality, three-dimensional, anti-aliased shaded color images into the frame buffer of a video display system. The method includes a parallel algorithm for rendering an important graphic primitive for accomplishing the production of a smoothly shaded color three-dimensional triangle with anti-aliased edges. By taking advantage of the SIMD architecture and said parallel algorithm, the very time consuming pixel by pixel computations are broken down for parallel execution. A single coordinate processor computes and transmits an overall triangle record which is essentially the same for all blocks of pixels within a given bounding box which box in turn surrounds each triangle. The individual pixel data is produced by a group of M. times. N pixel processors and stored in the frame buffer in a series of repetitive steps wherein each step corresponds to the processing of an M. times.

40400344, Aug 2, 1977

Dec 4, 1975

5/637492

Laszlo Antal Belady - Yorktown Heights NY
Carlo John Evangelisti - Jefferson Valley NY

International Business Machines Corporation - Armonk NY

G06F 104

364200

A data security system employing an automatic time-stamping mechanism for stamping a current time code in a data storage area or register associated with each storage section of a memory or an auxiliary storage device, such that each data read or write in a memory storage section updates the time code device. For every storage section of a memory, there is a time stamp storage element associated with it. Similarly, there is a time stamp storage element associated with every data channel. Whenever a storage section of memory is read from or written into the time stamp in the form of a unique binary number from a clock, indicating the current time of day and the date, is inserted into the time stamp storage element associated with that memory storage section. Examination of the contents of each time stamp storage element enables determination of whe the last read or write in a storage section occurred. A full memory address register is used to read or write data in the memory while only special high order bits of the memory address register are used to read or write the time stamp storage element associated with the memory storage section.