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Carl Edward Forhan

from Rochester, MN
Age ~54
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Also known as:
Carl E Forhan, Carl Te Forhan, Carl D Forhan, Carl A Forhan
Phone and address:
1736 Chippewa Dr, Rochester, MN 55901
(507) 288-5369
Related to:
Emma GranumMildred LarsonMark Hirning, 41Carol L Miller, 81Thomas Kowalski, 95
Connected to:
Christopher C Forhan, 64Craig A Forhan, 53James W Forhan, 71Joan A Forhan, 86John W Forhan, 62Michael A Forholt, 57Danielle M Forier, 45Kelsey L Forier, 34Dana M Forillo, 39Alicia B Forinash, 47

Carl Forhan Phones & Addresses

  • 1736 Chippewa Dr, Rochester, MN 55901 (507) 288-5369
  • 1774 10Th St, Rochester, MN 55904 (507) 288-5369
  • Memphis, TN
  • Sainte Genevieve, MO
  • 1736 Chippewa Dr NW, Rochester, MN 55901 (507) 279-9567

Work

Position: Sales Occupations

Education

Degree: Bachelor's degree or higher

Resumes

Resumes

Carl Forhan Photo 1

Senior Firmware Manager

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Location:
Rochester, MN
Industry:
Computer Hardware
Work:
LSI since Mar 2011
Senior Firmware Manager
Songbird Productions since Jan 1999
Owner
LSI Apr 2010 - Mar 2011
Firmware Manager
LSI Jan 2009 - Apr 2010
System Validation Manager
LSI May 2008 - Jan 2009
Technical Firmware Manager
Education:
Christian Brothers University 1988 - 1992
BSEE
Skills:
Firmware
Embedded Systems
Debugging
Device Drivers
Embedded Software
Rtos
Soc
Scsi
Software Development
C
Hardware
Sata
Ic
Engineering Management
Software Engineering
Ssd
Arm
Usb
Pcie
Algorithms
Serial Ata
C (Programming Language
Distributed Team Management
Project Management
Coaching
Professional Mentoring
Carl Forhan Photo 2

Senior Firmware Manager At Lsi

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Position:
Senior Firmware Manager at LSI, Owner at Songbird Productions
Location:
Rochester, Minnesota Area
Industry:
Computer Hardware
Work:
LSI since Mar 2011
Senior Firmware Manager
Songbird Productions since Jan 1999
Owner
LSI Apr 2010 - Mar 2011
Firmware Manager
LSI Jan 2009 - Apr 2010
System Validation Manager
LSI May 2008 - Jan 2009
Technical Firmware Manager
Education:
Christian Brothers University 1988 - 1992
BSEE
Skills:
Engineering Management
Firmware
Embedded Systems
Embedded Software
Debugging
Device Drivers
SCSI

Publications

Us Patents

Advanced Read Cache Management

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US Patent:
6338115, Jan 8, 2002
Filed:
Feb 16, 1999
Appl. No.:
09/250349
Inventors:
Robert Edward Galbraith - Rochester MN
Carl E. Forhan - Rochester MN
Jessica M. Gisi - Rochester MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1200
US Classification:
711113, 711136, 711137, 711160, 711213
Abstract:
A low complexity approach to DASD cache management. Large, fixed-size bands of data from the DASD, rather than variable size records or tracks, are managed, resulting in reduced memory consumption. Statistics are collected for bands of data, as well as conventional LRU information, in order to improve upon the performance of a simple LRU replacement scheme. The statistics take the form of a single counter which is credited (increased) for each read to a band and penalized (reduced) for each write to a band. Statistics and LRU information are also collected for at least half as many nonresident bands as resident bands. In an emulation mode, control information (e. g. , statistics and LRU information) regarding potentially cacheable DASD data, is collected even though there is no cache memory installed. When in this mode, the control information permits a real time emulation of performance enhancements that would be achieved were cache memory added to the computer system. Dynamic reconfiguration of the cache size is also permitted in real time without requiring computer system downtime.

Method And System For Maintaining Data Coherency In A Dual Input/Output Adapter Utilizing Clustered Adapters

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US Patent:
6530003, Mar 4, 2003
Filed:
Jul 26, 2001
Appl. No.:
09/916022
Inventors:
Brian Eric Bakke - Rochester MN
Carl Edward Forhan - Rochester MN
Robert Edward Galbraith - Rochester MN
Jessica Gisi - Rochester MN
Frederic Lawrence Huss - Rochester MN
Daniel Frank Moertl - Rochester MN
Douglas David Prigge - Kenyon MN
Paul Gary Reuland - Rochester MN
Timothy Jerry Schimke - Oronoco MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1120
US Classification:
711162, 711118, 711112, 711113, 714 6, 707204
Abstract:
A method for maintaining data coherency in a dual Input/Output(I/O) adapter having primary and secondary adapters, wherein each of the primary and secondary adapters includes resident write cache data and directory storage devices. The method includes utilizing a split point to separate each of the cache data and directory storage devices into first and second regions, wherein the first regions contain the primary adapter cache data and directory information and the second regions contain the secondary adapter cache data and directory information. Information stored in the primary adapter cache data and directory storage devices is mirrored into the secondary adapter cache data and directory storage devices or, alternatively, information stored in the secondary adapter cache data and directory storage devices is mirrored into the primary adapter cache data and directory storage devices utilizing a dedicated communication link, such as a high-speed serial bus, between the primary and secondary adapters.

Advanced Read Cache Management

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US Patent:
6877065, Apr 5, 2005
Filed:
Aug 23, 2001
Appl. No.:
09/935939
Inventors:
Robert Edward Galbraith - Rochester MN, US
Carl E. Forhan - Rochester MN, US
Jessica M. Gisi - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F012/00
US Classification:
711113, 711136, 711137, 711160
Abstract:
A low complexity approach to DASD cache management. Large, fixed-size bands of data from the DASD, rather than variable size records or tracks, are managed, resulting in reduced memory consumption. Statistics are collected for bands of data, as well as conventional LRU information, in order to improve upon the performance of a simple LRU replacement scheme. The statistics take the form of a single counter which is credited (increased) for each read to a band and penalized (reduced) for each write to a band. Statistics and LRU information are also collected for at least half as many nonresident bands as resident bands. In an emulation mode, control information (e. g. , statistics and LRU information) regarding potentially cacheable DASD data, is collected even though there is no cache memory installed. When in this mode, the control information permits a real time emulation of performance enhancements that would be achieved were cache memory added to the computer system. Dynamic reconfiguration of the cache size is also permitted in real time without requiring computer system downtime.

Method And System For Improved Buffer Utilization For Disk Array Parity Updates

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US Patent:
7290199, Oct 30, 2007
Filed:
Nov 19, 2004
Appl. No.:
10/994086
Inventors:
Carl Edward Forhan - Rochester MN, US
Robert Edward Galbraith - Rochester MN, US
Adrian Cuenin Gerhard - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 29/00
US Classification:
714770, 711114, 719325
Abstract:
During a parity update of a parity stripe in a disk array, constant values used in finite field arithmetic are algebraically combined in order to reduce the number of buffers and steps needed to update multiple parity values when a change in data occurs. In one implementation, for example, the contents of a buffer that stores the product of a delta value associated with the change in data and a first constant, which is used to update a first parity value, are multiplied by a value representative of the ratio of a second constant, which is used to update a second parity value, and the first constant.

Method And System For Recovering From Abnormal Interruption Of A Parity Update Operation In A Disk Array System

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US Patent:
7392428, Jun 24, 2008
Filed:
Nov 19, 2004
Appl. No.:
10/994097
Inventors:
Carl Edward Forhan - Rochester MN, US
Robert Edward Galbraith - Rochester MN, US
Adrian Cuenin Gerhard - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 11/00
US Classification:
714 15, 714 6, 714 19
Abstract:
Data associated with the state of a parity update operation in a disk array system such as a RAID-6 system is stored during performance of the operation so that, in the event the operation is interrupted, recovery may be initiated using the stored data. The stored data may include a state indicator that is indicative of the status of the parity update operation, and snapshot data (e. g. , a delta value indicative of a difference between new and old data) captured during the parity update operation.

Method And System For Enhanced Error Identification With Disk Array Parity Checking

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US Patent:
7392458, Jun 24, 2008
Filed:
Nov 19, 2004
Appl. No.:
10/994088
Inventors:
Carl Edward Forhan - Rochester MN, US
Robert Edward Galbraith - Rochester MN, US
Adrian Cuenin Gerhard - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03M 13/00
US Classification:
714770, 711114, 719325
Abstract:
When parity checking in a disk array such as a RAID-6 system determines data and parity information is unsynchronized, additional calculations are performed to determine whether the error may be attributed to faulty data on a disk drive or to a more systemic problem such as a faulty controller. In particular, for each particular error detected, the parity generating information is analyzed to determine if each error involves a common disk index. If so, the data can be corrected on that disk; if not other corrective procedures are implemented.

Recovering From Abnormal Interruption Of A Parity Update Operation In A Disk Array System

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US Patent:
7487394, Feb 3, 2009
Filed:
Apr 21, 2008
Appl. No.:
12/106856
Inventors:
Carl Edward Forhan - Rochester MN, US
Robert Edward Galbraith - Rochester MN, US
Adrian Cuenin Gerhard - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 11/00
US Classification:
714 15, 714 6, 714 19
Abstract:
Data associated with the state of a parity update operation in a disk array system such as a RAID-6 system is stored during performance of the operation so that, in the event the operation is interrupted, recovery may be initiated using the stored data. The stored data may include a state indicator that is indicative of the status of the parity update operation, and snapshot data (e. g. , a delta value indicative of a difference between new and old data) captured during the parity update operation.

Method And System For Increasing Parallelism Of Disk Accesses When Restoring Data In A Disk Array System

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US Patent:
7669107, Feb 23, 2010
Filed:
Oct 24, 2007
Appl. No.:
11/923280
Inventors:
Carl Edward Forhan - Rochester MN, US
Robert Edward Galbraith - Rochester MN, US
Adrian Cuenin Gerhard - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 29/00
US Classification:
714763, 714768, 714770
Abstract:
In a disk array environment such as a Redundant Array of Independent Disks-6 (RAID-6) environment, the overall performance overhead associated with exposed mode operations such as resynchronization, rebuild and exposed mode read operations is reduced through increased parallelism. By selecting only subsets of the possible disks required to solve a parity stripe equation for a particular parity stripe, accesses to one or more disks in a disk array may be omitted, thus freeing the omitted disks to perform other disk accesses. In addition, disk accesses associated with different parity stripes may be overlapped such that the retrieval of data necessary for restoring data for one parity stripe is performed concurrently with the storage of restored data for another parity stripe.
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Carl Edward Forhan from Rochester, MN, age ~54 Get Report