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Cameron E Luce

from Colchester, VT
Age ~39
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Related to:
Robyn L Standring, 59Timothy StandringBernardo J Difloures, 63
Connected to:
Ana L Luce, 54Brad W Luce, 43Brian R Luce, 45Bruce S Luce, 61Cacee M Luce, 40Carl O Luce, 76Charlene C Luce, 68Charles L Luce, 62Chelsey R Luce, 32Christopher M Luce, 60

Cameron Luce Phones & Addresses

  • 823 Main St, Colchester, VT 05446
  • 831 Main St, Colchester, VT 05446
  • Essex Junction, VT
  • Underhill, VT
  • 60 Brickyard Rd UNIT 27, Essex Junction, VT 05452

Publications

Us Patents

Through Silicon Via Wafer And Methods Of Manufacturing

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US Patent:
20130334701, Dec 19, 2013
Filed:
Jun 19, 2012
Appl. No.:
13/527131
Inventors:
Jeffrey P. GAMBINO - Westford VT, US
Jessica A. LEVY - Milton VT, US
Cameron E. LUCE - Essex Junction VT, US
Daniel S. VANSLETTE - Fairfax VT, US
Bucknell C. WEBB - Yorktown Heights NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H01L 23/48
H01L 21/768
US Classification:
257774, 438667, 257E21586, 257E23011
Abstract:
A through silicon via with sidewall roughness and methods of manufacturing the same are disclosed. The method includes forming a via in a substrate and roughening a sidewall of the via by depositing material within the via. The method further includes removing a backside of the substrate to form a through via with a roughened sidewall structure.

Semiconductor Structure With Semiconductor-On-Insulator Region And Method

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US Patent:
20230125584, Apr 27, 2023
Filed:
Sep 22, 2022
Appl. No.:
17/934220
Inventors:
- Malta NY, US
Alvin J. Joseph - Williston VT, US
Siva P. Adusumilli - South Burlington VT, US
Cameron Luce - Colchester VT, US
International Classification:
H01L 21/02
Abstract:
Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

Avalanche Photodiode

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US Patent:
20210320217, Oct 14, 2021
Filed:
Apr 9, 2020
Appl. No.:
16/844606
Inventors:
- SANTA CLARA CA, US
Siva P. ADUSUMILLI - South Burlington VT, US
John J. ELLIS-MONAGHAN - Grand Isle VT, US
Vibhor JAIN - Williston VT, US
Ramsey HAZBUN - Colchester VT, US
Pernell DONGMO - Essex Junction VT, US
Cameron E. LUCE - Colchester VT, US
Steven M. SHANK - Jericho VT, US
Rajendran KRISHNASAMY - Essex Junction VT, US
International Classification:
H01L 31/107
H01L 31/0376
H01L 31/028
H01L 31/18
Abstract:
The present disclosure relates to semiconductor structures and, more particularly, to an avalanche photodiode and methods of manufacture. The structure includes: a substrate material having a trench with sidewalls and a bottom composed of the substrate material; a first semiconductor material lining the sidewalls and the bottom of the trench; a photosensitive semiconductor material provided on the first semiconductor material; and a third semiconductor material provided on the photosensitive semiconductor material.

Epitaxial Growth Constrained By A Template

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US Patent:
20210296122, Sep 23, 2021
Filed:
Mar 17, 2020
Appl. No.:
16/821228
Inventors:
- Santa Clara CA, US
Cameron Luce - Colchester VT, US
Ramsey Hazbun - Colchester VT, US
Mark Levy - Williston VT, US
Anthony K. Stamper - Williston VT, US
Alvin J. Joseph - Williston VT, US
International Classification:
H01L 21/02
H01L 21/324
H01L 21/762
Abstract:
Methods of forming structures with electrical isolation. A dielectric layer is formed over a semiconductor substrate, openings are patterned in the dielectric layer that extend to the semiconductor substrate, and a semiconductor material is epitaxially grown from portions of the semiconductor substrate that are respectively exposed inside the openings. The semiconductor material, during growth, defines a semiconductor layer that includes first portions respectively coincident with the openings and second portions that laterally grow from the first portions to merge over a top surface of the dielectric layer. A modified layer containing a trap-rich semiconductor material is formed in the semiconductor substrate.

Semiconductor Structure With Semiconductor-On-Insulator Region And Method

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US Patent:
20210287902, Sep 16, 2021
Filed:
Mar 11, 2020
Appl. No.:
16/815070
Inventors:
- Santa Clara CA, US
Alvin J. Joseph - Williston VT, US
Siva P. Adusumilli - South Burlington VT, US
Cameron Luce - Colchester VT, US
Assignee:
GLOBALFOUNDRIES U.S. Inc. - Santa Clara CA
International Classification:
H01L 21/02
Abstract:
Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

Heterojunction Bipolar Transistors

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US Patent:
20210091195, Mar 25, 2021
Filed:
Jan 2, 2020
Appl. No.:
16/732755
Inventors:
- Santa Clara CA, US
Vibhor JAIN - Williston VT, US
Qizhi LIU - Lexington MA, US
Ramsey HAZBUN - Colchester VT, US
Pernell DONGMO - Essex Junction VT, US
John J. PEKARIK - Underhill VT, US
Cameron E. LUCE - Colchester VT, US
International Classification:
H01L 29/423
H01L 29/66
H01L 29/737
H01L 29/08
Abstract:
The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the sub-collector region, the collector region composed of semiconductor material; an intrinsic base region composed of intrinsic base material surrounded by the semiconductor material above the collector region; and an emitter region above the intrinsic base region.

Sealed Cavity Structures With A Planar Surface

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US Patent:
20190363160, Nov 28, 2019
Filed:
Aug 12, 2019
Appl. No.:
16/538062
Inventors:
- Grand Cayman, KY
Anthony K. STAMPER - Burlington VT, US
Laura J. SCHUTZ - Richmond VT, US
Cameron E. Luce - Colchester VT, US
International Classification:
H01L 29/06
H01L 29/78
H01L 21/762
H01L 21/84
H01L 27/12
Abstract:
The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture. The structure includes a cavity formed in a substrate material and which has a curvature at its upper end. The cavity is covered with epitaxial material that has an upper planar surface.

Heterojunction Bipolar Transistors With An Inverted Crystalline Boundary In The Base Layer

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US Patent:
20190326411, Oct 24, 2019
Filed:
Apr 24, 2018
Appl. No.:
15/961364
Inventors:
- Grand Cayman, KY
Pernell Dongmo - Essex Junction VT, US
Cameron Luce - Colchester VT, US
James W. Adkisson - Jericho VT, US
Qizhi Liu - Lexington MA, US
International Classification:
H01L 29/66
H01L 29/737
H01L 29/06
H01L 29/08
H01L 29/10
Abstract:
Fabrication methods and device structures for a heterojunction bipolar transistor. A trench isolation region is formed that surrounds an active region of semiconductor material, a collector is formed in the active region, and a base layer is deposited that includes a first section over the trench isolation region, a second section over the active region, and a third section over the active region that connects the first section and the second section. An emitter is arranged over the second section of the base layer, and an extrinsic base layer is arranged over the first section of the base layer and the third section of the base layer. The extrinsic base layer includes a first section containing polycrystalline semiconductor material and a second section containing single-crystal semiconductor material. The first and second sections of the extrinsic base layer intersect along an interface that extends over the trench isolation region.
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Cameron E Luce from Colchester, VT, age ~39 Get Report