Search

Bulent I Dervisoglu

from Mountain View, CA
Age ~77
Get Report
Also known as:
Bulent Ismail Dervisoglu, Bulent Te Dervisoglu, Bulent R Dervisoglu, Bulent U, Bulent I
Phone and address:
495 Sleeper Ave, Mountain View, CA 94040
(650) 428-0411
Related to:
Ergin DervisogluFunda Dervisoglu, 49Cigdem Dervisoglu, 77
Connected to:
Siranoush Dervogormiyaciyan, 47Galina P Derweduwen, 73Allen J Derwent, 97Edward R Derwent, 72Andrea J Derwin, 59David J Derwin, 72Elizabeth M Derwin, 70Jayne E Derwin, 76Laura A Derwin, 51Robert J Derwin, 61

Bulent Dervisoglu Phones & Addresses

  • 495 Sleeper Ave, Mountain View, CA 94040 (650) 428-0411 (650) 964-3398
  • 78 Angelica Dr, Framingham, MA 01701
  • North Woodstock, NH
  • 495 Sleeper Ave, Mountain View, CA 94040 (415) 706-3469

Work

Position: Protective Service Occupations

Education

Degree: High school graduate or higher

Emails

b***[email protected]

Resumes

Resumes

Bulent Dervisoglu Photo 1

Bulent Dervisoglu

View page

Business Records

Name / Title
Company / Classification
Phones & Addresses
Bulent I. Dervisoglu
President
INTERNATIONAL BUSINESS CONSULTANTS, INC
78 Angelica Dr, Framingham, MA 01701
495 Sleeper Ave, Mountain View, CA 94040
Bulent I. Dervisoglu
President
ON-CHIP TECHNOLOGIES, INC
495 Sleeper Ave, Mountain View, CA 94040
Bulent I. Dervisoglu
Principal
Technologies On Chip Inc
Business Services at Non-Commercial Site
495 Sleeper Ave, Mountain View, CA 94040

Publications

Us Patents

Method And Apparatus For Providing Optimized Access To Circuits For Debug, Programming, And Test

View page
US Patent:
6594802, Jul 15, 2003
Filed:
Nov 20, 2000
Appl. No.:
09/716583
Inventors:
Michael Ricchetti - Nashua NH
Christopher J. Clark - Durham NH
Bulent I. Dervisoglu - Mountain View CA
Assignee:
Intellitech Corporation - Durham NC
International Classification:
G06F 1750
US Classification:
716 4, 716 16, 714727
Abstract:
An access interface for accessing electrical nodes of an electronic circuit for programming, testing, and debugging the electronic circuit. The access interface includes a protocol generator and a data generator that may be programmed to apply control and/or data sequences directly to the electronic circuit. The access interface performs operational commands based upon a plurality of states included in a programmable state machine. By suitably programming the protocol generator, the data generator, and the state machine, electrical nodes of the electronic circuit can be accessed in reduced time using a reduced number of operations. The access interface is controlled by a test resource apparatus, which communicates with the electronic circuit connected to the access interface. The access interface may be implemented as a downloadable circuit, e. g. , it may be programmed into a programmable logic device by the test resource apparatus.

Hierarchical Test Circuit Structure For Chips With Multiple Circuit Blocks

View page
US Patent:
6631504, Oct 7, 2003
Filed:
Apr 19, 2001
Appl. No.:
09/839602
Inventors:
Bulent Dervisoglu - Mountain View CA
Laurence H. Cooke - Los Gatos CA
Assignee:
Cadence Design Systems, Inc - San Jose CA
International Classification:
G06F 1750
US Classification:
716 4, 716 1
Abstract:
A system and method for testing an integrated circuit having internal circuit blocks. Each of the internal circuit blocks may have its own test circuit block, referred to as a socket access port. The integrated circuit preferably includes a chip access port (e. g. , an IEEE standard 1149. 1 compliant test access port) connected to a set of boundary-scan cells, and connected in a hierarchical fashion to the lower-level test circuit blocks. Each of the lower-level test control circuit blocks preferably comprises a socket access port controller, and test operation is transferred downward and upwards within said hierarchical structure by communicating from a test control circuit block to the test control circuit block at the immediately higher or immediately lower level in the hierarchical structure. Each of the lower-level test control circuit blocks of the hierarchical test control network may be functionally identical. Further, each of the lower-level test control circuit blocks may be structurally identical.

On-Chip Service Processor For Test And Debug Of Integrated Circuits

View page
US Patent:
6687865, Feb 3, 2004
Filed:
Mar 24, 1999
Appl. No.:
09/275726
Inventors:
Bulent Dervisoglu - Mountain View CA
Laurence H. Cooke - Los Gatos CA
Vacit Arat - Los Altos Hills CA
Assignee:
On-Chip Technologies, Inc. - Los Altos Hills CA
International Classification:
G01R 3128
US Classification:
714726, 714727, 714729
Abstract:
An integrated circuit is described which include a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface, or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

Hierarchical Test Circuit Structure For Chips With Multiple Circuit Blocks

View page
US Patent:
6816996, Nov 9, 2004
Filed:
Dec 20, 2002
Appl. No.:
10/327369
Inventors:
Bulent Dervisoglu - Mountain View CA
Laurence H. Cooke - Los Gatos CA
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 1750
US Classification:
716 4, 716 1
Abstract:
A system and method for testing an integrated circuit having internal circuit blocks. Each of the internal circuit blocks may have its own test circuit block, referred to as a socket access port. The integrated circuit preferably includes a chip access port (e. g. , an IEEE standard 1149. 1 compliant test access port) connected to a set of boundary-scan cells, and connected in a hierarchical fashion to the lower-level test circuit blocks. Each of the lower-level test control circuit blocks preferably comprises a socket access port controller, and test operation is transferred downward and upwards within said hierarchical structure by communicating from a test control circuit block to the test control circuit block at the immediately higher or immediately lower level in the hierarchical structure. Each of the lower-level test control circuit blocks of the hierarchical test control network may be functionally identical. Further, each of the lower-level test control circuit blocks may be structurally identical.

Hierarchical Test Circuit Structure For Chips With Multiple Circuit Blocks

View page
US Patent:
6886121, Apr 26, 2005
Filed:
Jan 18, 2001
Appl. No.:
09/765958
Inventors:
Bulent Dervisoglu - Mountain View CA, US
Laurence H. Cooke - Los Gatos CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G01R031/28
G06F017/50
US Classification:
714726, 716 4
Abstract:
A hierarchical test control network for an integrated circuit includes a top-level test control circuit block having a chip access port (CAP) controller. The hierarchical test control network also has multiple lower-level test control circuit blocks connected to the top-level test control circuit block in a hierarchical structure. Each of the lower-level test control circuit blocks are a socket access port (SAP) controller. Test operation is transferred downward and upwards within said hierarchical structure.

On-Chip Service Processor

View page
US Patent:
6964001, Nov 8, 2005
Filed:
Jan 30, 2004
Appl. No.:
10/767265
Inventors:
Bulent Dervisoglu - Mountain View CA, US
Laurence H. Cooke - Los Gatos CA, US
Vacit Arat - La Canada Flintridge CA, US
Assignee:
On-Chip Technologies, Inc. - Los Gatos CA
International Classification:
G01R031/28
US Classification:
714726, 714727, 714729
Abstract:
An integrated circuit is described which include a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface, or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

On-Chip Service Processor

View page
US Patent:
7080301, Jul 18, 2006
Filed:
Oct 31, 2005
Appl. No.:
11/261762
Inventors:
Bulent Dervisoglu - Mountain View CA, US
Laurence H. Cooke - Los Gatos CA, US
Vacit Arat - La Canada Flintridge CA, US
Assignee:
On-Chip Technologies, Inc. - Los Gatos CA
International Classification:
G01R 31/28
US Classification:
714733, 714726
Abstract:
An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

Hierarchical Test Circuit Structure For Chips With Multiple Circuit Blocks

View page
US Patent:
7181705, Feb 20, 2007
Filed:
Dec 20, 2002
Appl. No.:
10/327369
Inventors:
Bulent Dervisoglu - Mountain View CA, US
Laurence H. Cooke - Los Gatos CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 4, 716 5, 716 8, 716 10
Abstract:
A system and method for testing an integrated circuit having internal circuit blocks. Each of the internal circuit blocks may have its own test circuit block, referred to as a socket access port. The integrated circuit preferably includes a chip access port (e. g. , an IEEE standard 1149. 1 compliant test access port) connected to a set of boundary-scan cells, and connected in a hierarchical fashion to the lower-level test circuit blocks. Each of the lower-level test control circuit blocks preferably comprises a socket access port controller, and test operation is transferred downward and upwards within said hierarchical structure by communicating from a test control circuit block to the test control circuit block at the immediately higher or immediately lower level in the hierarchical structure. Each of the lower-level test control circuit blocks of the hierarchical test control network may be functionally identical. Further, each of the lower-level test control circuit blocks may be structurally identical.
Control profile
Bulent I Dervisoglu from Mountain View, CA, age ~77 Get Report