Bryce D Horine

6353539, Mar 5, 2002

Jul 21, 1998

09/120517

Bryce D. Horine - Aloha OR
Michael W. Leddige - Beaverton OR

Intel Corporation - Santa Clara CA

H05K 702

361736, 361784, 361763, 361765, 361803, 257723, 257686, 439638, 365 63, 22818021

A printed circuit board includes a first component mounted on a first side of the printed circuit board. A second component has an identical pin-out as the first component. The second component is mounted on a second side of the printed circuit board. A first signal line connects a first landpad coupled to a first contact on the first component with a second landpad coupled to a corresponding first contact on the second component. A second signal line connects a third landpad coupled to a second contact on the first component with a fourth land pad coupled to a corresponding second contact on the second component. The first signal line has is equal in length to the second signal line.

6362973, Mar 26, 2002

Mar 14, 2000

09/524627

Michael W. Leddige - Beaverton OR
Bryce D. Horine - Aloha OR

Intel Corporation - Santa Clara CA

H05K 102

361762, 361772, 333 32, 333246, 174266, 174255

A multi-layer printed circuit board that includes a first layer and a second layer that have first and second signal traces, respectively. The multi-layer printed circuit board includes a via that couples a signal transmitting component to the second signal trace and a throttling member, which is coupled to the first signal trace. The throttling member reduces the speed at which a first signal routed over the first signal trace travels when compared to the speed at which that signal would have traveled had the throttling member been absent.

6366466, Apr 2, 2002

Mar 14, 2000

09/524450

Michael W. Leddige - Beaverton OR
Bryce D. Horine - Aloha OR
James A. McCall - Beaverton OR

Intel Corporation - Santa Clara CA

H05K 102

361760, 361777, 361736, 361720, 257775, 257773, 174261

A multi-layer printed circuit board that includes a first layer and a second layer that have first and second signal traces, respectively. The first signal trace has a relatively thin section and a relatively thick section. The multi-layer printed circuit board also includes a via that couples the first signal trace to the second signal trace. The first signal traces relatively thin section is located between its relatively thick section and the via.

6429383, Aug 6, 2002

Apr 14, 1999

09/291724

John T. Sprietsma - Hillsboro OR
Steve Joy - Portland OR
Bryce Horine - Aloha OR

Intel Corporation - Santa Clara CA

H05K 116

174260, 174261, 29852, 257698, 361807

A circuit board includes electrical interconnect mounting pads for mounting electronic devices thereto. Some of the electrical interconnect mounting pads include a plated through hole which traverses through the circuit board. One end of the plated through holes is closed, plugged or covered to prevent migration of solder through the plated through holes during a solder operation. The reduction in solder migration, as a result of plugging the plated through hole, increases solder joint quality over solder joint quality achieved using plated through holes which are not closed at one end.

6477614, Nov 5, 2002

Sep 8, 2000

09/658293

Michael W. Leddige - Beaverton OR
Bryce D. Horine - Aloha OR
Randy Bonella - Portland OR
Peter D. MacWilliams - Aloha OR

Intel Corporation - Santa Clara CA

G06F 1206

711 5, 711115, 711170, 710131, 714 56

A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus. A method includes determining whether a memory device to which signals are addressed is on a first memory module. Signals are routed to a first memory bus on the first memory module connected to the memory device if the memory is on the first memory module. Signals are routed to a second memory bus on a second memory module if the memory device is not on the first memory module.

6587912, Jul 1, 2003

Sep 30, 1998

09/163860

Michael W. Leddige - Beaverton OR
Bryce D. Horine - Aloha OR
Randy Bonella - Portland OR
Peter D. MacWilliams - Aloha OR

Intel Corporation - Santa Clara CA

G06F 1200

711 5, 709249, 710131

A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus.

6674648, Jan 6, 2004

Jul 23, 2001

09/911754

James A. McCall - Beaverton OR
Bryce D. Horine - Beaverton OR

Intel Corporation - Santa Clara CA

H05K 706

361788, 361760, 361777, 361782, 361786, 361803, 174261

In some embodiments, the invention includes a termination card having a substrate having groups of fingers on a first side of the substrate and groups of fingers on a second side of the substrate and wherein some of the groups of fingers on the first side and some of the groups of fingers on the second side are connected through module connectors, and others of the groups of fingers on the first side are coupled to on module terminations on the first side.

6803527, Oct 12, 2004

Mar 26, 2002

10/108127

Terrance J. Dishongh - Hillsboro OR
Bryce Horine - Beaverton OR

Intel Corporation - Santa Clara CA

H05K 116

174260, 174262, 29832, 29842

A circuit board apparatus and a method for a circuit board. An embodiment of a circuit board includes a first layer and a second layer; a substrate between the first layer and the second layer; a first surface mount device pad on the first layer of the substrate; a first via, the first via being formed partially or wholly through a first end of the first surface mount device pad, the first via passing through the substrate between the first layer and the second layer; a second surface mount device pad adjacent to the first surface mount device pad; and a second via, the second via being formed partially or wholly through a first end of the second surface mount device pad, the second via passing through the substrate, the first end of the first surface mount device pad being the end of the first surface mount device pad that is the farthest from the first end of the second surface mount device pad.