Inventors:
Suresh Chemudupati - Marlborough MA, US
Victor T. Lau - Marlborough MA, US
Bruno DiPlacido - Westborough MA, US
Eric J. DeHaemer - Shrewsbury MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 11/00
US Classification:
714 43, 714 4, 714 39, 709220, 709230
Abstract:
A device, method, and system are disclosed. In one embodiment, the device comprises one or more error receiving units, each operable to receive error requests from a given layer in a protocol and synchronize the received error requests to a common clock domain for all layers, and an arbiter unit operable to receive the synchronized error requests from the one or more error receiving units, encode the error requests onto on a common error interconnect, and route the encoded error requests across the interconnect to configuration space.
