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Brian Towles Phones & Addresses

  • 2122 Meares Rd, Chapel Hill, NC 27514
  • Raleigh, NC
  • New York, NY
  • 1200 Dale Ave, Mountain View, CA 94040
  • 121 Campus Dr, Stanford, CA 94305
  • Atlanta, GA
  • Lakewood, WA

Work

Company: Trafigura work and learn business center Mar 2012 Position: Assembler

Education

School / High School: Stamford High School- Stamford, CT 2008 Specialities: Bank

Resumes

Resumes

Brian Towles Photo 1

Computer Architect And Asic Engineer

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Location:
2122 Meares Rd, Chapel Hill, NC 27514
Industry:
Computer Hardware
Work:
Google
Computer Architect and Asic Engineer

D. E. Shaw Research
Research Engineer
Education:
Stanford University 1999 - 2004
Doctorates, Doctor of Philosophy, Engineering
Georgia Institute of Technology 1995 - 1999
Skills:
High Performance Computing
Computer Architecture
Algorithms
C
Parallel Computing
Asic
Python
Verilog
C++
Vlsi
Simulations
Microprocessors
Fpga
Signal Processing
Soc
Brian Towles Photo 2

Brian Towles

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Brian Towles Photo 3

Brian Towles Stamford, CT

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Work:
Trafigura Work and Learn Business Center

Mar 2012 to 2000
Assembler

Trafigura Work and Learn Business Center

Oct 2012 to Jan 2013
Trafigura Culinary Food Prep

Trafigura Work and Learn Business Center
Stamford, CT
Jun 2012 to Sep 2012
Customer Service

CED It Off Cleaning Services
Bronx, NY
Jun 2009 to Jun 2009

Education:
Stamford High School
Stamford, CT
2008 to 2000
Bank

Publications

Us Patents

Routing With Virtual Channels

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US Patent:
7809006, Oct 5, 2010
Filed:
Aug 12, 2008
Appl. No.:
12/190210
Inventors:
Brian Patrick Towles - New York NY, US
Assignee:
D. E. Shaw Research, LLC - New York NY
International Classification:
H04L 12/28
H04L 12/56
US Classification:
370406, 370405
Abstract:
An approach to introducing adaptive routing into a communication approach for passing messages between nodes over links between the nodes includes forming virtual channels over the links of the system and defining a deterministic routing function over the virtual channels such that the deterministic routing function is deadlock free. Adaptive routing is then permitted at nodes using the existing virtual channels by introducing a constraint on the available virtual channels used to forward communication that arrives at a node for a particular destination. The constraint on the virtual channels is such that the adaptive system is also deadlock free.

Scheduling Connections In A Multi-Stage Switch To Retain Non-Blocking Properties Of Constituent Switching Elements

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US Patent:
20030214944, Nov 20, 2003
Filed:
Feb 19, 2003
Appl. No.:
10/370037
Inventors:
Brian Towles - Stanford CA, US
Assignee:
Velio Communications, Inc. - Milpitas CA
International Classification:
H04Q011/00
US Classification:
370/388000, 370/386000
Abstract:
A scheduling algorithm is provided that may be implemented in a multi-stage switch requiring less switching elements than known switching architectures in order to increase bandwidth and to retain the non-blocking properties of the constituent switching elements for incoming traffic, including multicast traffic. A scheduling algorithm is also provided for incremental scheduling of connections being added or removed from the switch.

Link And Physical Coding Sub-Layer Protocols

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US Patent:
20100195835, Aug 5, 2010
Filed:
Feb 4, 2010
Appl. No.:
12/699959
Inventors:
Larry Nociolo - Fair Haven NJ, US
Brian Patrick Towles - New York NY, US
Assignee:
D.E. Shaw Research, LLC - New York NY
International Classification:
H04K 1/00
US Classification:
380287
Abstract:
An approach to data communication makes use of a protocol for encoding data on a serial link that provides both a run length limiting function and a frame marking function, while minimizing communication overhead over the data bearing portions of the signal, and while limiting latency introduced into the communication. In some examples, a single bit is added as a frame marker in such a way that a single bit frame marker also limits run length.

Connecting Processors Using Twisted Torus Configurations

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US Patent:
20230094933, Mar 30, 2023
Filed:
Nov 28, 2022
Appl. No.:
18/070040
Inventors:
- Mountain View CA, US
Brian Patrick Towles - Chapel Hill NC, US
International Classification:
H04L 41/12
H04L 49/10
H04L 49/15
H04L 67/10
Abstract:
Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for connecting processors using twisted torus configurations. In some implementations, a cluster of processing nodes is coupled using a reconfigurable interconnect fabric. The system determines a number of processing nodes to allocate as a network within the cluster and a topology for the network. The system selects an interconnection scheme for the network, where the interconnection scheme is selected from a group that includes at least a torus interconnection scheme and a twisted torus interconnection scheme. The system allocates the determined number of processing nodes of the cluster in the determined topology, sets the reconfigurable interconnect fabric to provide the selected interconnection scheme for the processing nodes in the network, and provides access to the network for performing a computing task.

Inverse Weighted Arbitration

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US Patent:
20150365329, Dec 17, 2015
Filed:
Jun 15, 2015
Appl. No.:
14/739177
Inventors:
- New York NY, US
Brian Patrick Towles - New York NY, US
International Classification:
H04L 12/803
H04L 12/911
H04L 12/851
H04L 12/933
Abstract:
A data communication apparatus includes a router, first and second packet producers, and a penalizer. The router is directly connected to the first and second producers. The penalizer assesses penalties against each producer whenever that producer is serviced. The penalty value depends at least in part on an expected extent to which the first producer requires service. The penalizer then accumulates penalties against each producer.

Isbn (Books And Publications)

Principles and Practices of Interconnection Networks

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Author

Brian Towles

ISBN #

0122007514

Brian P Towles from Chapel Hill, NC, age ~48 Get Report