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Brian G Curran

from Saugerties, NY
Age ~56
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Also known as:
Brian Currain
Related to:
Lonnie Y Lum, 60Judith E Conrad, 81Joseph D Bohn, 57Liza M Bohn, 57Kevin G Houlihan, 57John S Lum, 86Jessica Nickowal, 53
Connected to:
Adara M Curran, 34Amber D Curran, 51Bailey M Curran, 35Belinda G Curran, 68Bernadette M Curran, 76Brenna R Curran, 36Bret T Curran, 76Candy Curran, 66Carl C Curran, 89Carlos C Curran, 43

Brian Curran Phones & Addresses

  • Saugerties, NY
  • 16 Rossmore Ave, Bronxville, NY 10708 (914) 779-4919
  • 40 Cook Ave, Yonkers, NY 10701
  • Kingston, NY
  • 215 Dean St, Brooklyn, NY 11217 (718) 596-2574
  • Pikesville, MD
  • Plainsboro, NJ
  • Everett, MA
  • Columbus, OH

Work

Company: Hogan Lovells US LLP Address:

Specialities

International Trade and Investment

Professional Records

License Records

Brian J Curran

License #:
2806 - Expired
Issued Date:
Jan 22, 1986
Expiration Date:
May 1, 1994
Type:
Limited LP Installer

Lawyers & Attorneys

Brian Curran Photo 1

Brian Patrick Curran, Carle Place NY - Lawyer

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Address:
2 Douglas St, Carle Place, NY 11514
Licenses:
New York - Currently registered 1985
Education:
Hofstra University School of Law
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Brian Patrick Curran - Lawyer

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Licenses:
New Jersey - Active 1985
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Brian Patrick Curran - Lawyer

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Licenses:
Virginia - Authorized to practice law 2006
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Brian Francis Curran, Mineola NY - Lawyer

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Address:
Nicolini, Paradise, Ferritti & Sabella
114 Old Country Rd Ste 500, Mineola, NY 11501
(516) 741-6355 (Office)
Licenses:
New York - Currently registered 1995
Education:
Cuny Law School
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Brian Curran - Lawyer

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Office:
Hogan Lovells US LLP
Specialties:
International Trade and Investment
ISLN:
922015787
Admitted:
2008
University:
American University, School of International Service, M.A., 1995; The College of William and Mary, B.A., 1992
Law School:
The Georgetown university Law school, J.D., 2006

Business Records

Name / Title
Company / Classification
Phones & Addresses
Brian Curran
Owner
ENERGY SERVICES PROVIDER GROUP
Accountant · Human Resource Consulting Svcs
8005 Harford Rd, Parkville, MD 21234
(410) 332-0644, (410) 576-2260
Brian Curran
Principal
Mid Hudson Kennel Association, Ltd
Membership Organization
27 Saxton Flt Rd, West Saugerties, NY 12477
Brian Curran
DISCOVERIST VENTURES LLC

Publications

Us Patents

Clock Distribution With Constant Delay Clock Buffer Circuit

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US Patent:
6426661, Jul 30, 2002
Filed:
Aug 20, 2001
Appl. No.:
09/933193
Inventors:
Brian W. Curran - Saugerties NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 514
US Classification:
327263, 327262, 327278
Abstract:
A voltage-compensated, constant delay clock buffer for a chip clock distribution circuit employs a variable gain circuit to dynamically control the delay through the first inverter stage. In the presence of no voltage rail collapse the first stage gain is set high which results in a nominal delay through the first stage. As voltage rail collapse occurs local to the clock buffer circuit, the gain on the first stage is reduced to yield a smaller than nominal delay through the first stage in such a way as to compensate for the increased delay in the subsequent stage or stages. The control circuit is responsive to a first voltage rail and a second voltage rail to provide dynamic control of the delay through the first inverter stage. The circuit can compensate the circuit to handle a plurality of second inverter stages with the control circuit adjusting the delay of said first inverter stage, and with the control circuit remaining responsive to a first voltage rail and a second voltage rail.

High Performance, Low Power Differential Latch

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US Patent:
6657471, Dec 2, 2003
Filed:
Nov 8, 2002
Appl. No.:
10/290649
Inventors:
Brian W. Curran - Saugerties NY
Edward T. Malley - Fishkill NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 706
US Classification:
327211, 327212, 327 55
Abstract:
An improved pull-down latch circuit is provided for better latch performance. Previous pull-down latch circuit performance is compromised during pull-up operation since weak PFETs are employed to pull up latch nodes. A pull up assist circuit is incorporated to assist weak PFET when latch node is being pulled up. The assist circuit is isolated from latch circuit when latch node is being pull down to guarantee that pull down circuit can overcome pull-up circuit (for correct latch operation).

Frequency Doubling Two-Phase Clock Generation Circuit

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US Patent:
6661262, Dec 9, 2003
Filed:
Jun 20, 2002
Appl. No.:
10/177323
Inventors:
Brian W. Curran - Saugerties NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03B 1900
US Classification:
327116, 327119
Abstract:
A clock generation circuit globally distributes a half-frequency clock and doubles the clock frequency locally in a local clock block circuit. The circuit contains several subcircuits which detect the global clock edges (transitions), double the clock frequency and generate two shaped local clocks. A rising edge detection circuit generates a pulse in response to a rising edge of the global clock. A falling edge detection circuit generates a pulse in response to a falling edge of the global clock. A master clock SR (set/reset) latch is reset in response to either pulse and a slave clock SR latch is set in response to either pulse. A delay circuit generates a delayed signal in response to the setting of the master clock SR latch. This delayed signal sets the master clock SR latch and resets the slave clock SR latch. The master clock latch output is repowered to drive the master latches and the slave clock latch output is repowered to drive the slave latches.

Low Power Reduced Voltage Swing Latch

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US Patent:
6768365, Jul 27, 2004
Filed:
Oct 18, 2002
Appl. No.:
10/274191
Inventors:
Brian W. Curran - Saugerties NY
Edward T. Malley - Fishkill NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 104
US Classification:
327291, 327295
Abstract:
An improved clocking circuit is provided for generating a half swing clock. Previous circuit operations required an additional supply voltage rail (Vdd/2), but the preferred embodiment exploits charge sharing to generate a half swing clock with less power and without the additional supply voltage rail. To drive clock nodes to Vdd/2, a shunt transistor is opened, and the fully charged clock node shares its charge with the fully discharged clock node. When capacitances have been properly matched, both nodes will settle at Vdd/2.

Method For Statically Timing Soi Devices And Circuits

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US Patent:
6816824, Nov 9, 2004
Filed:
Apr 19, 1999
Appl. No.:
09/294178
Inventors:
Brian W. Curran - Saugerties NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
703 14, 703 4, 703 20, 703 2, 703 13, 716 6
Abstract:
Low-conductance and high-conductance IV characteristics (models) are created using the low and high end of their body voltage ranges, respectively. The body voltage of the device (FET) is initialized to the low end of range at time zero, and then a transient, two dimensional sweep of gate and drain voltages is performed. Drain currents are measured in this two dimensional region and are used to create a piecewise, linear IV model of device. The process is repeated for the highest body voltage. This process differs significantly from prior art bulk device characterization techniques, which did not have to initialize body voltage or perform a transient analysis. The body voltage is modulating during the switching event due to the gate-to-body and diffusion-to-body coupling; and thus only a transient analysis can properly model these coupling effects.

Low Power Overdriven Pass Gate Latch

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US Patent:
6882205, Apr 19, 2005
Filed:
Nov 8, 2002
Appl. No.:
10/290636
Inventors:
Brian W. Curran - Saugerties NY, US
Edward T. Malley - Fishkill NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F001/04
US Classification:
327291, 361 911
Abstract:
A clocking circuit decreases the load on the local clock signals to save power. The load is decreased by altering the structure of the latches. Typically, a passgate style latch is used where both an NFET and a PFET are used to control dataflow. Here, the PFET has been removed and the load is decreased. However, it is difficult to pass a logical through an NFET and this increases both the rising slew and rising edge delay through the latch. The effect is mitigated, though, by overdriving the local clock block (LCB) local clocks to drive a local clock to the latches by passgates using only NFET transistors in the master latches and slave latches. Overdrivig the NFET gate allows the NFET to pass a full-level logical signal.

Cmos Tapered Gate And Synthesis Method

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US Patent:
6966046, Nov 15, 2005
Filed:
Apr 24, 2001
Appl. No.:
09/841505
Inventors:
Brian W. Curran - Saugerties NY, US
Lisa Bryant Lacey - Clinton Corners NY, US
Gregory A. Northrop - Putnam Valley NY, US
Ruchir Puri - New Rochelle NY, US
Leon Stok - Croton-on-Hudson NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F017/50
US Classification:
716 18, 716 6
Abstract:
A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce the delay through some of the input pins. For example in a tapered NAND gate the bottom devices in the NFET stack are have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies the input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of the timing critical paths. The latest arriving gate input net is swapped with the net connected to the top pin. The gate is then converted to a tapered gate provided the paths through the bottom gate input(s) that are not timing critical.

Instruction Group Formation And Mechanism For Smt Dispatch

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US Patent:
7237094, Jun 26, 2007
Filed:
Oct 14, 2004
Appl. No.:
10/965143
Inventors:
Brian William Curran - Saugerties NY, US
Brian R. Konigsburg - Austin TX, US
Hung Qui Le - Austin TX, US
David Arnold Luick - Rochester MN, US
Dung Quoc Nguyen - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/38
US Classification:
712213, 712215, 712216
Abstract:
A more efficient method of handling instructions in a computer processor, by associating resource fields with respective program instructions wherein the resource fields indicate which of the processor hardware resources are required to carry out the program instructions, calculating resource requirements for merging two or more program instructions based on their resource fields, and determining resource availability for simultaneously executing the merged program instructions based on the calculated resource requirements. Resource vectors indicative of the required resource may be encoded into the resource fields, and the resource fields decoded at a later stage to derive the resource vectors. The resource fields can be stored in the instruction cache associated with the respective program instructions. The processor may operate in a simultaneous multithreading mode with different program instructions being part of different hardware threads.

Isbn (Books And Publications)

The Egyptian Renaissance: The Afterlife of Ancient Eygpt in Early Modern Italy

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Author

Brian A. Curran

ISBN #

0226128938

Vanishing Histories : 100 Endangered Sites from the World Monuments Watch

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Author

Brian A. Curran

ISBN #

0810914352

St. Petersburg

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Author

Brian Curran

ISBN #

0711224927

Wikipedia References

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Brian Curran

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Brian F. Curran

Control profile
Brian G Curran from Saugerties, NY, age ~56 Get Report