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Brian J Cleereman

from Folsom, CA
Age ~46
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Also known as:
Brian James Cleereman, Brian Katherine Cleereman, Brian J Cleerman, Brian N
Related to:
Larry Gant, 67Michelle Atwood, 48Melissa Morgan, 36Christopher Grant, 41
Connected to:
Joan A Cleereman, 64Karen M Cleereman, 58Nancy C Cleeremans, 72Alyssa R Clees, 33Catherine M Clees, 61Faith C Cleeter, 46Kimberly J Cleeter, 59Denise L Cleeton, 68James E Cleeve, 60Elisabeth Cleffi, 40

Brian Cleereman Phones & Addresses

  • Folsom, CA
  • 1914 Stafford St, Santa Clara, CA 95050
  • 2250 Monroe St, Santa Clara, CA 95050 (408) 564-5618
  • 4427 E Tanoak Dr, Boise, ID 83716 (208) 629-8227
  • West Chester, OH
  • Fremont, CA
  • Champaign, IL
  • Evanston, IL

Work

Company: Intel corporation Nov 1, 2001 Position: Senior principal engineer

Education

School / High School: University of Illinois at Urbana - Champaign Jan 1, 1997 to 2001

Skills

Process Integration • Silicon • Semiconductors • Design of Experiments • Jmp • Semiconductor Industry • Thin Films • Characterization • Ic • Simulations • Materials Science • Spc • Nand • Failure Analysis • Cmos

Languages

English

Industries

Semiconductors

Resumes

Resumes

Brian Cleereman Photo 1

Senior Principal Engineer

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Location:
116 Boxford Sq, Folsom, CA 95630
Industry:
Semiconductors
Work:
Intel Corporation
Senior Principal Engineer
Pratt & Whitney 2000 - 2000
Coop and Intern
Education:
University of Illinois at Urbana - Champaign Jan 1, 1997 - 2001
Skills:
Process Integration
Silicon
Semiconductors
Design of Experiments
Jmp
Semiconductor Industry
Thin Films
Characterization
Ic
Simulations
Materials Science
Spc
Nand
Failure Analysis
Cmos
Languages:
English

Publications

Us Patents

Methods Of Forming Memory; And Methods Of Forming Vertical Structures

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US Patent:
8609489, Dec 17, 2013
Filed:
Jun 6, 2011
Appl. No.:
13/154259
Inventors:
David A. Kewley - Boise ID, US
Brian Cleereman - Boise ID, US
Stephen W. Russell - Boise ID, US
Rex Stone - Albuquerque NM, US
Anthony C. Krauth - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21/336
US Classification:
438264, 438313, 257E21038, 257E21023, 257E21024, 257206, 257E21027
Abstract:
Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

Methods Of Forming Memory Cells; And Methods Of Forming Vertical Structures

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US Patent:
20110003469, Jan 6, 2011
Filed:
Jul 2, 2009
Appl. No.:
12/497128
Inventors:
David A. Kewley - Boise ID, US
Brian Cleereman - Boise ID, US
Stephen W. Russell - Boise ID, US
Rex Stone - Albuquerque NM, US
Anthony C. Krauth - Boise ID, US
International Classification:
H01L 21/28
H01L 21/768
US Classification:
438591, 438669, 438585, 257E21575, 257E2121, 257E2119
Abstract:
Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

Three Dimensional Nand Flash With Self-Aligned Select Gate

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US Patent:
20140003148, Jan 2, 2014
Filed:
Jun 27, 2012
Appl. No.:
13/534295
Inventors:
Jie Sun - Boise ID, US
Brian Cleereman - Boise ID, US
Minsoo Lee - Boise ID, US
International Classification:
H01L 27/088
H01L 21/336
G11C 16/04
US Classification:
36518517, 257 66, 36518505, 438287, 257E2706, 257E21423
Abstract:
An integrated circuit may include a pillar of semiconductor material, a field effect transistor having a channel that is formed in the pillar of semiconductor material, and two or more memory cells, stacked vertically on top of the field effect transistor, and having channels that are formed in the pillar semiconductor of material.

Three Dimensional Memory

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US Patent:
20220181483, Jun 9, 2022
Filed:
Feb 23, 2022
Appl. No.:
17/678971
Inventors:
- Boise ID, US
Hongbin Zhu - Boise ID, US
Gordon A. Haller - Boise ID, US
Roger W. Lindsay - Boise ID, US
Andrew Bicksler - Nampa ID, US
Brian J. Cleereman - Boise ID, US
Minsoo Lee - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 29/788
H01L 29/66
H01L 29/792
H01L 27/11524
H01L 27/11556
H01L 27/1157
H01L 27/11582
H01L 21/285
H01L 23/535
Abstract:
A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

Block-To-Block Isolation And Deep Contact Using Pillars In A Memory Array

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US Patent:
20230036595, Feb 2, 2023
Filed:
Feb 8, 2020
Appl. No.:
17/791176
Inventors:
- Santa Clara CA, US
Brian J. CLEEREMAN - Boise ID, US
Srivardhan GOWDA - Boise ID, US
Jui-Yen LIN - Hillsboro OR, US
Liu LIU - Dalian, CN
Krishna PARAT - Palo Alto CA, US
Jong Sun SEL - Dalian, CN
Baosuo ZHOU - Redwood CA, US
International Classification:
H01L 27/11582
H01L 27/11575
G11C 16/08
Abstract:
An integrated circuit memory includes a first memory block and an adjacent second memory block. The first memory block comprises a first memory pillar around which a first memory cell is formed. The second memory block comprises a second memory pillar around which a second memory cell is formed. An isolation or slit area between the first and second memory blocks electrically isolates the first and second memory blocks. In an example, the slit area comprising a slit pillar around which no memory cells are formed. The slit pillar is a dummy pillar, and insulator material electrically isolates the slit pillar from a Word Line (WL) through which it passes. The isolation layer electrically can also isolate a (WL) of the first memory block from a corresponding WL of the second memory block. In an example, the slit pillar and the memory pillars have at least in part similar structures.

Three Dimensional Memory

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US Patent:
20200243677, Jul 30, 2020
Filed:
Apr 10, 2020
Appl. No.:
16/845793
Inventors:
- Boise ID, US
Hongbin Zhu - Boise ID, US
Gordon A. Haller - Boise ID, US
Roger W. Lindsay - Boise ID, US
Andrew Bicksler - Nampa ID, US
Brian J. Cleereman - Boise ID, US
Minsoo Lee - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 29/788
H01L 23/535
H01L 21/285
H01L 29/792
H01L 27/11582
H01L 27/1157
H01L 27/11556
H01L 27/11524
H01L 29/66
Abstract:
A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

Integrated Structures And Methods Of Forming Vertically-Stacked Memory Cells

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US Patent:
20190229126, Jul 25, 2019
Filed:
Apr 1, 2019
Appl. No.:
16/371988
Inventors:
- Boise ID, US
Gordon A. Haller - Boise ID, US
Charles H. Dennison - San Jose CA, US
Anish A. Khandekar - Boise ID, US
Brett D. Lowe - Boise ID, US
Lining He - Singapore, SG
Brian Cleereman - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27/11556
H01L 27/1157
H01L 27/11582
H01L 27/11524
Abstract:
Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.

Methods And Apparatuses Having Memory Cells Including A Monolithic Semiconductor Channel

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US Patent:
20190131315, May 2, 2019
Filed:
Sep 17, 2018
Appl. No.:
16/132984
Inventors:
- Boise ID, US
Zhenyu Lu - Boise ID, US
Roger W. Lindsay - Boise ID, US
Brian Cleereman - Boise ID, US
John Hopkins - Meridian ID, US
Hongbin Zhu - Boise ID, US
Fatam Arzum Simsek-Ege - Boise ID, US
Prasanna Srinivasan - Boise ID, US
Purnima Narayanan - Boise ID, US
International Classification:
H01L 27/11582
H01L 27/1157
G11C 16/04
H01L 27/11556
H01L 29/66
H01L 27/11524
H01L 29/788
Abstract:
Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.
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Brian J Cleereman from Folsom, CA, age ~46 Get Report