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Brett E Huff

from Keller, TX
Age ~59
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Also known as:
Brett Eldon Huff, Brett Anne Huff, Brett A Huff, Brett F Huff, Brett G Huff, Katlyn Huff
Related to:
Laurie Davis, 48Corie AllfordU Ware, 67Ruby WareJames Hible, 62
Connected to:
Aleigh Huff, 32Alexa R Huff, 30Ali B Huff, 51Alicia Huff, 45Allyson M Huff, 36Alma A Huff, 80Amanda Huff, 41Andre Huff, 72Arthur L Huff, 78Asia Huff, 34

Brett Huff Phones & Addresses

  • Keller, TX
  • Napa, CA
  • 20715 Garden Place Ct, Cupertino, CA 95014 (510) 612-8670
  • Newark, CA
  • 790 Gable Cmn, Fremont, CA 94539 (510) 651-3570 (510) 797-9461
  • 40495 Chapel Way #22, Fremont, CA 94538
  • 360 Camphor Ave, Fremont, CA 94539
  • Babbitt, MN
  • Ironton, MN
  • Sunnyvale, CA
  • Santa Clara, CA

Resumes

Resumes

Brett Huff Photo 1

Principle Engineer Si Photonics

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Location:
790 Gable Dr, Fremont, CA 94539
Industry:
Semiconductors
Work:
Intel Corporation
Test Lab Manager
Stanford University May 2012 - Jul 2013
Snf Clean Room Manager
Sri International Aug 2009 - May 2012
Microfab Manager
Intel Corporation May 1988 - Aug 2009
Engineer
Intel/Ctm 1989 - 2009
Engineer
Education:
University of Minnesota 1985 - 1988
Bethel University 1983 - 1985
Skills:
Research
Brett Huff Photo 2

Brett Huff

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Brett Huff Photo 3

Brett Huff

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Brett Huff Photo 4

Brett Huff

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Brett Huff Photo 5

Brett Huff

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Brett Huff Photo 6

Brett Huff

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Brett Huff Photo 7

Brett Huff

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Publications

Us Patents

Methods For Forming Microtips In A Field Emission Device

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US Patent:
6572425, Jun 3, 2003
Filed:
Mar 28, 2001
Appl. No.:
09/820338
Inventors:
Michael A. Maxim - San Jose CA
Oleh Karpenko - San Jose CA
Brett E. Huff - Fremont CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01J 902
US Classification:
445 24, 445 50
Abstract:
Electron emission structures formed using standard semiconductor processes on a substrate first prepared with a topographical feature are disclosed. At least one layer of a first material is concurrently deposited on the substrate and etched from the substrate to form an atomically sharp feature. An at least one layer of a second material is deposited over the atomically sharp feature. A conductive layer is deposited over the at least one layer of the second material. A selected area of material is removed from the conductive layer and the at least one layer of second material to expose the atomically sharp feature. Finally, electrical connectivity is provided to elements of the electron emission structure.

Approach To Optimizing An Ild Argon Sputter Process

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US Patent:
6645353, Nov 11, 2003
Filed:
Dec 31, 1997
Appl. No.:
09/001350
Inventors:
Brett E. Huff - Fremont CA
Ken Schatz - Palo Alto CA
Mike Maxim - San Jose CA
William G. Petro - San Jose CA
Assignee:
Intel Corporation - Santa Clara
International Classification:
C23C 1435
US Classification:
20419232
Abstract:
A sputter etch system and a method of conducting a sputter etch. The sputter etch system includes an etch chamber with a wafer pedestal having a top surface to support a wafer and a magnet configured to provide a continuous magnetic field directed at the top surface of the wafer pedestal.

Design Structures Of And Simplified Methods For Forming Field Emission Microtip Electron Emitters

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US Patent:
6771011, Aug 3, 2004
Filed:
Mar 7, 2003
Appl. No.:
10/383966
Inventors:
Michael A. Maxim - San Jose CA
Oleh Karpenko - San Jose CA
Brett E. Huff - Fremont CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01J 1304
US Classification:
313309, 313310, 445 50
Abstract:
Electron emission structures formed using standard semiconductor processes on a substrate first prepared with a topographical feature are disclosed. At least one layer of a first material is concurrently deposited on the substrate and etched from the substrate to form an atomically sharp feature. An at least one layer of a second material is deposited over the atomically sharp feature. A conductive layer is deposited over the at least one layer of the second material. A selected area of material is removed from the conductive layer and the at least one layer of second material to expose the atomically sharp feature. Finally, electrical connectivity is provided to elements of the electron emission structure.

Methods Of Treating A Surface Of A Ferroelectric Media

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US Patent:
20080316897, Dec 25, 2008
Filed:
Jun 19, 2007
Appl. No.:
11/765250
Inventors:
Byong Man KIM - Fremont CA, US
Donald Edward ADAMS - Pleasanton CA, US
Brett Eldon HUFF - Fremont CA, US
Yevgeny V. ANOIKIN - Fremont CA, US
Robert N. STARK - Saratoga CA, US
Assignee:
NANOCHIP, INC. - Fremont CA
International Classification:
G11B 7/00
US Classification:
36911001
Abstract:
A method of forming a passivation layer over a ferroelectric layer of a ferroelectric media comprises introducing the ferroelectric layer to a plasma comprising one of oxygen, oxygen-helium, and oxygen-nitrogen-helium, etching a surface of the ferroelectric layer, forming one of a substantially oxygen enriched layer and a substantially hydroxyl enriched layer at the surface of the ferroelectric layer, introducing the ferroelectric layer to an environment comprising substantially nitrogen, and maintaining the ferroelectric layer within the environment so that nitrogen enriches the substantially oxygen enriched layer to form a passivation layer.

Surface-Treated Ferroelectric Media For Use In Systems For Storing Information

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US Patent:
20080318086, Dec 25, 2008
Filed:
Jun 19, 2007
Appl. No.:
11/765256
Inventors:
Byong Man Kim - Fremont CA, US
Donald Edward Adams - Pleasanton CA, US
Brett Eldon Huff - Fremont CA, US
Yevgeny V. Anoikin - Fremont CA, US
Robert N. Stark - Saratoga CA, US
Assignee:
NANOCHIP, INC. - Fremont CA
International Classification:
G11B 5/66
US Classification:
428827
Abstract:
A system for storing information comprises a media including a ferroelectric layer and a passivation layer formed over the ferroelectric layer, and a tip arranged in approximate contact with the passivation layer. The tip detects a polarization signal that corresponds to changes in polarization of domains of the ferroelectric layer.

Cantilever With Integral Probe Tip

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US Patent:
20090001488, Jan 1, 2009
Filed:
Jun 29, 2007
Appl. No.:
11/824509
Inventors:
John Magana - San Jose CA, US
Brett Huff - Fremont CA, US
International Classification:
H01L 27/14
H01L 21/02
US Classification:
257428, 438 57, 257E27122, 257E21002
Abstract:
In one embodiment, a metallic micro-cantilever, comprises a silicon substrate, at least one via plug extending from a surface of the silicon substrate, a metallic layer cantilevered from the at least one via plug, and a metallic probe tip extending from a surface of the metallic layer.

High Density Teos-Based Film For Intermetal Dielectrics

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US Patent:
53895819, Feb 14, 1995
Filed:
May 25, 1993
Appl. No.:
8/067335
Inventors:
Philip Freiberger - Santa Clara CA
Ragupathy V. Giridhar - San Jose CA
Brett Huff - Fremont CA
Farhad K. Moghadam - Los Gatos CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2190
US Classification:
437238
Abstract:
A method of forming a device and the device itself that utilizes a high density plasma-enhanced TEOS-based intermetal dielectric is disclosed. The high density is accomplished though the use of higher RF power and higher oxygen flow rate so that the TEOS is more completely oxidized. The higher density intermetal dielectric absorbs water from air slower than a standard intermetal dielectric film. This lower water absorbance reduces the amount of water in the device and reduces hot electron induced device degradation.

In-Situ Pre-Ild Deposition Treatment To Improve Ild To Metal Adhesion

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US Patent:
59501073, Sep 7, 1999
Filed:
Dec 17, 1996
Appl. No.:
8/768916
Inventors:
Brett E. Huff - Fremont CA
Farhad K. Moghadom - Los Gatos CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2144
US Classification:
438669
Abstract:
A method for improving interlayer dielectric to metal layer adhesion including an in-situ plasma treatment process. A metal layer which is formed on a substrate is treated with plasma prior to the deposition of the interlayer dielectric. The interlayer dielectric is deposited above the metal layer and contacts are formed through the interlayer dielectric which electrically connect the underlying metal layer to a subsequently formed metal layer. The plasma treatment step creates open molecular bonds on the surface of the metal layer which cause the interface between the metal layer and the interlayer dielectric to become more adhesive. Thus, decreasing the likelihood of delamination that degrades the electrical reliability of the device.
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Brett E Huff from Keller, TX, age ~59 Get Report