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Brent D Gilgen

from Boise, ID
Age ~71
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Also known as:
Brent Delon Gilgen, Brent B Gilgen, Brent D Bilgen, Brent Ailgen, Brent D Gilger, Bert Gilgen
Phone and address:
7000 Mcmullen St, Boise, ID 83709
(208) 377-2192
Related to:
Js LippincottJeff Lippincott, 74Megan Gilgen Butterfield, 41Martha E Gilgen, 69Lynn B Gilgen, 46Sharen L Evans, 84Matthew E Gilgen, 43Ruth A Lippincott, 76William K Evans, 84
Connected to:
Annette M Gilgenbach, 75Dana M Gilgenbach, 40Jeff D Gilgenbach, 38Kristen D Gilgenbach, 35Matthew R Gilgenbach, 42Muriel Gilgen, 40Thomas D Gilgenbach, 73Fay L Gilger, 97Keith E Gilger, 31Stephan W Gilges, 54

Brent Gilgen Phones & Addresses

  • 7000 Mcmullen St, Boise, ID 83709 (208) 377-2192 (208) 377-2199 (208) 841-8152
  • 6816 Fernwood Dr, Boise, ID 83709 (208) 371-2199
  • Meridian, ID
  • Juneau, AK
  • Eugene, OR

Work

Company: Micron technology Position: Engineer

Education

Degree: Bachelors, Bachelor of Science School / High School: University of Idaho 1980 to 1983 Specialities: Semiconductor Manufacturing

Skills

Ic • Semiconductors

Industries

Semiconductors

Resumes

Resumes

Brent Gilgen Photo 1

Engineer

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Location:
Boise, ID
Industry:
Semiconductors
Work:
Micron Technology
Engineer
Education:
University of Idaho 1980 - 1983
Bachelors, Bachelor of Science, Semiconductor Manufacturing
Skills:
Ic
Semiconductors

Publications

Us Patents

Controllable Ovonic Phase-Change Semiconductor Memory Device And Methods Of Fabricating The Same

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US Patent:
6423621, Jul 23, 2002
Filed:
Sep 25, 2001
Appl. No.:
09/964145
Inventors:
Trung T. Doan - Boise ID
D. Mark Durcan - Boise ID
Brent D. Gilgen - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2144
US Classification:
438597, 438 95, 438128, 438448, 257 3, 257 20, 257529, 257530
Abstract:
An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

Method For Fabricating A Small Area Of Contact Between Electrodes

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US Patent:
6462353, Oct 8, 2002
Filed:
Nov 2, 2000
Appl. No.:
09/703806
Inventors:
Brent Gilgen - Boise ID
Assignee:
Micron Technology Inc. - Boise ID
International Classification:
H01L 4700
US Classification:
257 3, 257 4, 257 5, 257 50, 257529, 257774, 257775
Abstract:
An electrode structure for use in a chalcogenide memory is disclosed. The electrode has a substantially frusto-conical shape, and is preferably formed by undercut etching a polysilicon layer beneath an oxide pattern. With this structure, improved current densities through the chalcogenide material can be achieved.

Compound Structure For Reduced Contact Resistance

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US Patent:
6688584, Feb 10, 2004
Filed:
May 16, 2001
Appl. No.:
09/858617
Inventors:
Ravi Iyer - Boise ID
Yongjun Jeff Hu - Boise ID
Luan Tran - Meridian ID
Brent Gilgen - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2940
US Classification:
258750, 258751
Abstract:
Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.

Controlable Ovonic Phase-Change Semiconductor Memory Device

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US Patent:
6781145, Aug 24, 2004
Filed:
Jul 9, 2002
Appl. No.:
10/191222
Inventors:
Trung T. Doan - Boise ID
D. Mark Durcan - Boise ID
Brent D. Gilgen - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
M01L 2904
US Classification:
257 3, 257 4, 257 41, 257 50, 257529, 257530
Abstract:
An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same are disclosed. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

Method For Fabricating A Memory Chip

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US Patent:
6825107, Nov 30, 2004
Filed:
Sep 25, 2001
Appl. No.:
09/963842
Inventors:
Trung T. Doan - Boise ID
D. Mark Durcan - Boise ID
Brent D. Gilgen - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2144
US Classification:
438597, 438 95, 438150, 438592, 257 20, 257529
Abstract:
An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

Capacitor For Use In An Integrated Circuit

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US Patent:
6888217, May 3, 2005
Filed:
Aug 30, 2001
Appl. No.:
09/945555
Inventors:
Brent Gilgen - Boise ID, US
Belford T. Coursey - Meridian ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L029/00
H01L021/00
US Classification:
257532, 438396
Abstract:
A capacitor including a first plate of conductive material that is formed in a predetermined shape. A layer of dielectric material is formed on at least a portion of the first plate and substantially conforms to the predetermined shape of the first plate. A second plate of conductive material is formed over the layer of dielectric material.

Methods For Preventing Cross-Linking Between Multiple Resists And Patterning Multiple Resists

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US Patent:
6893958, May 17, 2005
Filed:
Apr 26, 2002
Appl. No.:
10/133295
Inventors:
Belford T. Coursey - Meridian ID, US
Brent D. Gilgen - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L021/4763
US Classification:
438637, 438634, 438636, 438639
Abstract:
The present invention prevents cross-linking between multiple resists that are used in the fabrication of a semiconductor device. In order to prevent resists in close proximity or contact with one another from cross-linking, a non-reactive separation layer is disposed between the resists. The separation layer prevents incompatible components of the resists from reacting with one another. Forming the separation layer between the resists allows a resist located above the separation layer to be polymerized and patterned as desired without patterning another resist located below the separation layer. Methods of patterning multiple resists are also disclosed.

Controllable Ovanic Phase-Change Semiconductor Memory Device

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US Patent:
6897467, May 24, 2005
Filed:
Jan 17, 2003
Appl. No.:
10/346994
Inventors:
Trung T. Doan - Boise ID, US
D. Mark Durcan - Boise ID, US
Brent D. Gilgen - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L047/00
US Classification:
257 4, 257 3, 257 20, 257 41, 257 50, 257529
Abstract:
An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same, are disclosed. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.
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Brent D Gilgen from Boise, ID, age ~71 Get Report