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Brent M Ahlquist

from Loomis, CA
Age ~58
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Also known as:
Brent Michael Ahlquist, Brent M Ahiquist, Brent Ahlguist
Phone and address:
5165 Val Verde Rd, Loomis, CA 95650
(916) 652-2156
Related to:
Trudi Adele Ahlquist, 32Ruth Penksa, 97Lauren R Guarino, 31Douglas A Rein, 33Ronald Penksa, 72
Connected to:
Becky L Ahlquist, 73Jeffrey W Ahlquist, 46Jodi L Ahlquist, 48Justin C Ahlquist, 47Pearl A Ahlquist, 61Ronda D Ahlquist, 57Johan S Ahlqvist, 62Karl M Ahlqvist, 34Doris M Ahlrichs, 95Marcia E Ahlrichs, 80

Brent Ahlquist Phones & Addresses

  • 5165 Val Verde Rd, Loomis, CA 95650 (916) 652-2156
  • 6696 Crystal Springs Dr, San Jose, CA 95120
  • Lesterville, SD
  • Uncasville, CT
  • Goleta, CA
  • Sacramento, CA

Work

Company: Intel corporation Jun 2015 to Apr 2016 Position: Asic verification engineer

Education

Degree: Master of Science, Masters School / High School: Uc Santa Barbara 1994 to 1995 Specialities: Engineering

Skills

Asic Design and Verification • System Verilog • Systemverilog • Embedded Systems • Processors • Hardware Architecture • Unix • Asic • Soc • Device Drivers • Rtl Design • Python • Perl • Software Engineering • Flash Memory • Standards Development • Product Innovation • Hardware • Vlsi • Firmware • Debugging • Testing • Computer Architecture • Storage • Verilog • Application Specific Integrated Circuits

Interests

Coaching and Playing Soccer

Emails

b***[email protected]

Industries

Computer Hardware

Resumes

Resumes

Brent Ahlquist Photo 1

Brent Ahlquist

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Location:
San Jose, CA
Industry:
Computer Hardware
Work:
Intel Corporation Jun 2015 - Apr 2016
Asic Verification Engineer
Oracle Dec 2011 - Jun 2014
Senior Hardware Engineer
Numonyx Apr 2008 - Jun 2009
Flash Memory and Security Architect
Trusted Computing Group Dec 2006 - Sep 2008
Mobile Phone Workgroup
Omtp Feb 2006 - Apr 2008
Secure Boot Workgroup
Education:
Uc Santa Barbara 1994 - 1995
Master of Science, Masters, Engineering University of California, Berkeley 1987 - 1990
Bachelors, Bachelor of Science
Skills:
Asic Design and Verification
System Verilog
Systemverilog
Embedded Systems
Processors
Hardware Architecture
Unix
Asic
Soc
Device Drivers
Rtl Design
Python
Perl
Software Engineering
Flash Memory
Standards Development
Product Innovation
Hardware
Vlsi
Firmware
Debugging
Testing
Computer Architecture
Storage
Verilog
Application Specific Integrated Circuits
Interests:
Coaching and Playing Soccer

Publications

Us Patents

Default Instruction To Hide Nonvolatile Memory Core Initialization Latency

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US Patent:
7441069, Oct 21, 2008
Filed:
Apr 13, 2006
Appl. No.:
11/403742
Inventors:
Brent Ahlquist - Loomis CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711103
Abstract:
A memory operating in an execute-in-place (XIP) type mode returns a default instruction when an nV memory core is not ready for access. The default instruction may be selected to provide a system stall when executed within a corresponding processor.

Data Invalid Signal For Non-Deterministic Latency In A Memory System

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US Patent:
7571297, Aug 4, 2009
Filed:
Dec 30, 2005
Appl. No.:
11/323174
Inventors:
Geoffrey Gould - El Dorado Hills CA, US
Brent M. Ahlquist - Loomis CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711167
Abstract:
An apparatus, system, and method for a data invalid signal for non-deterministic latency in memory are described. The apparatus may include a memory to determine that data to be buffered for a data burst cannot be guaranteed in time to satisfy a deterministic latency parameter. The memory may provide an indication that the data cannot be guaranteed. Other embodiments are described and claimed.

Accelerating Integrity Checks Of Code And Data Stored In Non-Volatile Memory

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US Patent:
7743239, Jun 22, 2010
Filed:
Jun 30, 2006
Appl. No.:
11/480308
Inventors:
Brent M. Ahlquist - Loomis CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/14
G06F 9/44
US Classification:
713 1, 713165, 713189, 713190, 717114, 726 27, 726 32, 705 1, 711103
Abstract:
In some embodiments, a command may be used by a host processor to access certain information from a non-volatile memory, together with a message authentication code. That information may be utilized to generate a message authentication code on the processor. Then, in any future accesses, the message authentication code generated by the host processor may be compared to the message authentication code from the non-volatile memory to determine the integrity of data or code that is received from the non-volatile memory.

Low-Cost Pseudo-Random Nonce Value Generation System And Method

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US Patent:
7945790, May 17, 2011
Filed:
Dec 4, 2006
Appl. No.:
11/633952
Inventors:
Brent M. Ahlquist - Loomis CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 9/32
H04L 9/00
G06F 11/30
US Classification:
713193, 713189, 713190, 713191, 713192, 726 27, 726 28, 726 29, 726 30
Abstract:
Briefly, a low-cost system and method for pseudo-random nonce value generation is disclosed.

Method And Apparatus For An Always Open Write-Only Register Based Memory Mapped Overlay Interface For A Nonvolatile Memory

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US Patent:
8327087, Dec 4, 2012
Filed:
Dec 31, 2008
Appl. No.:
12/347962
Inventors:
Brent Ahlquist - Loomis CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G06F 12/00
US Classification:
711154, 711104, 711170, 711173
Abstract:
Methods and systems are provided that may include a controller comprising an access element and a command interface. Access element may provide access to a physical nonvolatile memory device. Physical nonvolatile memory device may have a default setting permitting a direct read operation of the physical nonvolatile memory device while prohibiting a direct write operation of the physical nonvolatile memory device. A command interface may modify access to the physical nonvolatile memory device by issuing a command through at least one write overlay window of a memory partition to change the default setting to write to the physical nonvolatile memory. The at least one write overlay window may be logically separate from at least one read overlay window of the memory partition.

Continuous Isochronous Read Access And Measurement Of Data Stored In Non-Volatile Memory

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US Patent:
8572374, Oct 29, 2013
Filed:
May 3, 2007
Appl. No.:
11/799989
Inventors:
Brent M. Ahlquist - Loomis CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 21/00
US Classification:
713168, 713162, 714819
Abstract:
A measurement and authentication engine in a nonvolatile memory computes an original hash value on data read from the nonvolatile memory. A measurement and authentication engine in a host processor recomputes the hash value on the data received from nonvolatile memory and checks that the computed hash value matches the hash value generated and transferred from the nonvolatile memory.

Storing Compressed Code On A Non-Volatile Memory

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US Patent:
20080001789, Jan 3, 2008
Filed:
Jun 29, 2006
Appl. No.:
11/478204
Inventors:
Lance W. Dover - Fair Oaks CA, US
Brent Ahlquist - Loomis CA, US
International Classification:
H03M 7/00
US Classification:
341 50
Abstract:
The time used in manufacturing an electronic device can be reduced by reducing the amount of time taken to store code on non-volatile memories. In one embodiment, storing compressed code to a non-volatile memory can reduce the manufacturing time of an electronic device. The code stored on the non-volatile memory can be decompressed by a controller in the electronic device and loaded on the non-volatile memory for execution by the electronic device.

Authenticating Data Returned From Non-Volatile Memory Commands

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US Patent:
20080082819, Apr 3, 2008
Filed:
Sep 28, 2006
Appl. No.:
11/529022
Inventors:
Jack Brizek - Placerville CA, US
Brent M. Ahlquist - Loomis CA, US
International Classification:
H04L 9/00
US Classification:
713168
Abstract:
In some embodiments, a command may be used by a host processor to access certain information from a non-volatile memory, together with a message authentication code. That information may be utilized to generate a message authentication code on the processor. Then, in any future accesses, the message authentication code generated by the host processor may be compared to the message authentication code from the non-volatile memory to determine the integrity of data or code that is received from the non-volatile memory.
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Brent M Ahlquist from Loomis, CA, age ~58 Get Report